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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin embedded processor adsp-bf522/adsp-bf523/adsp-bf524/ adsp-bf525/adsp-bf526/adsp-bf527 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features up to 600 mhz high performance blackfin processor two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of programming and comp iler-friendly support advanced debug, trace, an d performance monitoring accepts a wide range of supply voltages for internal and i/o operations. see specifications on page 28 programmable on-chip volt age regulator (adsp-bf523/ adsp-bf525/adsp-bf527 processors only) qualified for automotive applications. see automotive products on page 87 289-ball and 208-ball csp_bga packages memory 132k bytes of on-chip memory (see table 1 on page 3 for l1 and l3 memory size details) external memory controller wi th glueless support for sdram and asynchronous 8-bit and 16-bit memories flexible booting options from external flash, spi, and twi memory or from host devices including spi, twi, and uart code security with lockbox secure technology one-time-programmable (otp) memory memory management unit providing memory protection peripherals usb 2.0 high speed on-the-go (otg) with integrated phy ieee 802.3-compliant 10/100 ethernet mac parallel peripheral interface (ppi), supporting itu-r 656 video data formats host dma port (hostdp) 2 dual-channel, fu ll-duplex synchronous serial ports (sports), supporting eight stereo i 2 s channels 12 peripheral dmas, 2 mastered by the ethernet mac 2 memory-to-memory dmas with external request lines event handler with 54 interrupt inputs serial peripheral interface (spi) compatible port 2 uarts with irda support 2-wire interface (twi) controller eight 32-bit timers/counters with pwm support 32-bit up/down counter with rotary support real-time clock (rtc) and watchdog timer 32-bit core timer 48 general-purpose i/os (gpios), with programmable hysteresis nand flash controller (nfc) debug/jtag interface on-chip pll capable of frequency multiplication figure 1. processor block diagram sport0 timer0 voltage regulator* *regulator only available on adsp-bf523/adsp-bf525/adsp-bf527 processors port j gpio port h gpio port g gpio port f jtag test and emulation peripheral access bus otp memory counter watchdog timer rtc twi sport1 nfc ppi uart0 spi timer7 - 1 emac host dma boot rom dma access bus interrupt controller dma controller l1 data memory l1 instruction memory usb 16 dcb eab external port flash, sdram control b uart1 deb
rev. d | page 2 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table of contents features ................................................................. 1 memory ................................................................ 1 peripherals ............................................................. 1 general description ................................................. 3 portable low power architecture ............................. 3 system integration ................................................ 3 processor peripherals ............................................. 3 blackfin processor core .......................................... 4 memory architecture ............................................ 5 dma controllers .................................................. 9 host dma port .................................................... 9 real-time clock ................................................... 9 watchdog timer ................................................ 10 timers ............................................................. 10 up/down counter and thumbwheel interface .......... 10 serial ports ........................................................ 10 serial peripheral interface (spi) port ....................... 11 uart ports ...................................................... 11 twi controller interface ...................................... 12 10/100 ethernet mac .......................................... 12 ports ................................................................ 12 parallel peripheral interface (ppi) ........................... 13 usb on-the-go dual-role device controller ........... 14 code security with lockbox secure technology ......... 14 dynamic power management ................................ 14 adsp-bf523/adsp-bf525/adsp-bf527 voltage regulation ........................................... 16 adsp-bf522/adsp-bf524/adsp-bf526 voltage regulation ........................................... 16 clock signals ...................................................... 16 booting modes ................................................... 18 instruction set description .................................... 20 development tools .............................................. 20 additional information ........................................ 21 related signal chains ........................................... 22 lockbox secure technology disclaimer .................... 22 signal descriptions ................................................. 23 specifications ........................................................ 28 operating conditions for adsp-bf522/adsp-bf524/adsp-bf526 processors ...................................................... 28 operating conditions for adsp-bf523/adsp-bf525/ adsp-bf527 processors .................................... 30 electrical characteristics ....................................... 32 absolute maximum ratings ................................... 37 package information ............................................ 38 esd sensitivity ................................................... 38 timing specifications ........................................... 39 output drive currents ......................................... 73 test conditions .................................................. 75 environmental conditions .................................... 79 289-ball csp_bga ball assignment .. ......................... 80 208-ball csp_bga ball assignment .. ......................... 83 outline dimensions ................................................ 86 surface-mount design .......................................... 87 automotive products .............................................. 87 ordering guide ..................................................... 88 revision history 7/13rev. c to rev. d updated development tools .................................... 20 corrected footnote 9 and added footnote 11 in operating conditions for adsp-bf523/adsp-bf525/ adsp-bf527 processors .......................................... 30
rev. d | page 3 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 general description the adsp-bf52x processors are members of the blackfin fam- ily of products, incorporating the analog devices/intel micro signal architecture (msa). blackfin ? processors combine a dual-mac state-of-the-art signal processing engine, the advan- tages of a clean, orthogonal risc-like microprocessor instruction set, and single-ins truction, multiple-data (simd) multimedia capabili ties into a single instruction-set architecture. the adsp-bf52x processors are completely code compatible with other blackfin processors. the adsp-bf523/ adsp-bf525/adsp-bf527 processors offer performance up to 600 mhz. the adsp-bf522/adsp-bf524/adsp-bf526 pro- cessors offer performance up to 400 mhz and reduced static power consumption. di fferences with respect to peripheral combinations are shown in table 1 . by integrating a rich set of indu stry-leading system peripherals and memory, blackfin processors are the platform of choice for next-generation applications th at require risc-like program- mability, multimedia support , and leading-edge signal processing in one integrated package. portable low power architecture blackfin processors provide world-class power management and performance. they are produced with a low power and low voltage design methodology and feature on-chip dynamic power management, which is the ability to vary both the voltage and frequency of oper ation to significantl y lower overall power consumption. this capability can result in a substantial reduc- tion in power consum ption, compared with just varying the frequency of operation. this a llows longer battery life for portable appliances. system integration the adsp-bf52x processors are highly integrated system-on-a- chip solutions for the next generation of embedded network connected applications. by combining industry-standard inter- faces with a high performance signal processing core, cost- effective applications can be developed quickly, without the need for costly external comp onents. the system peripherals include an ieee-compliant 802.3 10/100 ethernet mac, a usb 2.0 high speed otg controller, a twi controller, a nand flash controller, two uart ports, an spi port, two serial ports (sports), eight general purpose 32-bit timers with pwm capa- bility, a core timer, a real-time clock, a watchdog timer, a host dma (hostdp) interface, and a parallel peripheral interface (ppi). processor peripherals the adsp-bf52x processors cont ain a rich set of peripherals connected to the core via severa l high bandwidth buses, provid- ing flexibility in system configuration as well as excellent overall system performance (see the block diagram on page 1 ). these blackfin processors co ntain dedicated network commu- nication modules and high speed serial and parallel ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or extern al sources, and power manage- ment control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. all of the peripherals, except fo r the general-purpose i/o, twi, real-time clock, and timers, are supported by a flexible dma structure. there are also separa te memory dma channels dedi- cated to data transfers between the processor's various memory spaces, including external sdram and asynchronous memory. multiple on-chip buses running at up to 133 mhz provide enough bandwidth to keep the processor core running along with activity on all of the on -chip and external peripherals. the adsp-bf523/adsp-bf525/adsp-bf527 processors include an on-chip voltage regula tor in support of the proces- sors dynamic power manageme nt capability. the voltage table 1. processor comparison feature adsp-bf522 adsp-bf524 adsp-bf526 adsp-bf523 adsp-bf525 adsp-bf527 host dma 111111 usb C 1 1 C 1 1 ethernet mac C C 1 C C 1 internal voltage regulator C C C 1 1 1 twi 111111 sports 222222 uarts 222222 spi 111111 gp timers 888888 gp counter 111111 watchdog timers 111111 rtc 111111 parallel peripheral interface 111111 gpios 48 48 48 48 48 48 memory (bytes) l1 instruction sram 48k 48k 48k 48k 48k 48k l1 instruction sram/cache 16k 16k 16k 16k 16k 16k l1 data sram 32k 32k 32k 32k 32k 32k l1 data sram/cache 32k 32k 32k 32k 32k 32k l1 scratchpad 4k 4k 4k 4k 4k 4k l3 boot rom 32k 32k 32k 32k 32k 32k maximum instruction rate 1 1 maximum instruction rate is not availabl e with every possible sclk selection. 400 mhz 600 mhz maximum system clock speed 100 mhz 133 mhz package options 289-ball csp_bga 208-ball csp_bga
rev. d | page 4 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 regulator provides a range of co re voltage levels when supplied from v ddext . the voltage regulator can be bypassed at the user's discretion. blackfin processor core as shown in figure 2 , the blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit data from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compar e/select and vector search instructions. for certain instructions, two 16- bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). if the second alu is used, quad 16-bit operations are possible. the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware is provided to support zero-over- head looping. the architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit provides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisting of four sets of 32-bit index, modify, figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 888 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory
rev. d | page 5 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the two data memories hold data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram and cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be operating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain system resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and co re resources. the blackfin processor instruct ion set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction instructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor assembly language uses an algebraic syn- tax for ease of coding and readability. the architecture has been optimized for use in conjunction with the c/c++ compiler, resulting in fast and effici ent software implementations. memory architecture the blackfin processor views memory as a single unified 4g byte address space, using 32- bit addresses. all resources, including internal memory, external memory, and i/o control registers, occupy separate sect ions of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low- latency on-chip memory as cache or sram, and larger, lower-co st and performance off-chip memory systems. see figure 3 . the on-chip l1 memory system is the highest-performance memory available to the blackfin processor. the off-chip memory system, acce ssed through the external bus interface unit (ebiu), provides expansio n with sdram, flash memory, and sram, optionally accessing up to 132m bytes of physical memory. the memory dma controller prov ides high-bandwidth data- movement capability. it can perform block transfers of code or data between the internal memory and the external memory spaces. internal (on-chip) memory the processor has three blocks of on-chip memory providing high-bandwidth access to the core. the first block is the l1 instruction memory, consisting of 64k bytes sram, of which 16k bytes can be configured as a four-way set-associative cache. this memory is accessed at full processor speed. the second on-chip memory block is the l1 data memory, con- sisting of up to two banks of up to 32k bytes each. each memory bank is configurable, offering both cache and sram functional- ity. this memory block is accessed at full processor speed. the third memory block is a 4k byte scratchpad sram which runs at the same speed as the l1 memories, but is only accessible as data sram and cannot be configured as cache memory. external (off-chip) memory external memory is accessed via the ebiu. this 16-bit interface provides a glueless connection to a bank of synchronous dram (sdram), as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. figure 3. internal/external memory map reserved core mmr registers (2m bytes) reserved scratchpad sram (4k bytes) instruction bank b sram (16k bytes) system mmr registers (2m bytes) reserved reserved data bank b sram / cache (16k bytes) data bank b sram (16k bytes) data bank a sram / cache (16k bytes) async memory bank 3 (1m bytes) async memory bank 2 (1m bytes) async memory bank 1 (1m bytes) async memory bank 0 (1m bytes) sdram memory (16m bytes 128m bytes) instruction sram / cache (16k bytes) in t er n a l m em o r y m ap e x te r na l m e m o r y m a p 0xffff ffff 0xffe0 0000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xff90 8000 0xff90 4000 0xff80 8000 0xff80 4000 0x2040 0000 0x2030 0000 0x2020 0000 0x2010 0000 0x2000 0000 0xef00 0000 0x0000 0000 0xffc0 0000 0xffb0 1000 0xffa0 0000 data bank a sram (16k bytes) 0xff90 0000 0xff80 0000 reserved reserved 0xffa0 c000 0xffa0 8000 instruction bank a sram (32k bytes) reserved boot rom (32k bytes) 0xef00 8000 reserved 0x08 00 0000
rev. d | page 6 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 the sdram controller ca n be programmed to interface to up to 128m bytes of sdram. a separate row can be open for each sdram internal bank and the sdram controller supports up to 4 internal sdram banks, improving overall performance. the asynchronous memory cont roller can be programmed to control up to four banks of devices with very flexible timing requirements for a wide variety of devices. each bank occupies a 1m byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1m byte of memory. nand flash controller (nfc) the adsp-bf52x processors provide a nand flash controller (nfc). nand flash devices pr ovide high-density, low-cost memory. however, nand flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. because of this, nand flash is often used for read- only code storage. in this case , all dsp code can be stored in nand flash and then transferred to a faster memory (such as sdram or sram) before execution. another common use of nand flash is for storage of multimedia files or other large data segments. in this case, a software file system may be used to manage reading and wr iting of the nand flash device. the file system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations. hardware features of the nfc include: ? support for page program, pa ge read, and block erase of nand flash devices, with accesses aligned to page boundaries. ? error checking and correction (ecc) hardware that facili- tates error detection and correction. ? a single 8-bit external bus interface for commands, addresses, and data. ? support for slc (single level cell) nand flash devices unlimited in size, with page sizes of 256 and 512 bytes. larger page sizes can be supported in software. ? capability of releasing external bus interface pins during long accesses. ? support for internal bus requests of 16 bits. ? dma engine to transfer data between internal memory and nand flash device. one-time programmable memory the processor has 64k bits of one-time programmable non- volatile memory that can be pr ogrammed by the developer only one time. it includes the array and logic to support read access and programming. additiona lly, its pages can be write protected. otp enables developers to store both public and private data on-chip. in addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-defin able data such as customer id, product id, mac address, etc. hence, generic parts can be shipped, which are then programmed an d protected by the developer within this non-volatile memory. i/o memory space the processor does not define a separate i/o space. all resources are mapped through the flat 32-bit address space. on-chip i/o devices have their control registers mapped into memory-mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting the processor contains a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. if the processor is configured to boot from boot rom memory space, the proces- sor starts executing from the on-chip boot rom. for more information, see booting modes on page 18 . event handling the event controller on the proc essor handles all asynchronous and synchronous events to the processor. the processor pro- vides event handling that supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. prioriti zation ensures th at servicing of a higher-priority event takes pr ecedence over servicing of a lower-priority event. the contro ller provides support for five different types of events: ? emulation an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset this event resets the processor. ? nonmaskable interrupt (nmi) the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. ? exceptions events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to comp lete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts events that occur asynchronously to program flow. they are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. each event type has an associated register to hold the return address and an associated return -from-event inst ruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the processor event controller consists of two stages, the core event controller (cec) and the system interrupt controller (sic). the core event controller works with the system interrupt
rev. d | page 7 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 controller to prioritize and cont rol all system events. conceptu- ally, interrupts from the peripher als enter into the sic and are then routed directly into the ge neral-purpose interrupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers, leav ing seven prioritized interrupt inputs to support the peripherals of the processor. table 2 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller provides the mapping and rout- ing of events from the many peri pheral interrupt sources to the prioritized general-purpose interrupt inputs of the cec. although the processor provides a default mapping, the user can alter the mappings and prioriti es of interrupt events by writ- ing the appropriate values into the interrupt assignment registers (sic_iarx). table 3 describes the inputs into the sic and the default mappings into the cec. table 2. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test controlemu 1reset rst 2 nonmaskable interrupt nmi 3exception evx 4 reserved 5 hardware error ivhw 6 core timer ivtmr 7 general-purpose interrupt 7 ivg7 8 general-purpose interrupt 8 ivg8 9 general-purpose interrupt 9 ivg9 10 general-purpose interrupt 10 ivg10 11 general-purpose interrupt 11 ivg11 12 general-purpose interrupt 12 ivg12 13 general-purpose interrupt 13 ivg13 14 general-purpose interrupt 14 ivg14 15 general-purpose interrupt 15 ivg15 table 3. system interrupt controller (sic) peripheral interrupt event general purpose interrupt (at reset )peripheral interrupt id default core interrupt id sic registers pll wakeup interrupt ivg7 0 0 iar0 imask0, isr0, iwr0 dma error 0 (generic) ivg7 1 0 iar0 imask0, isr0, iwr0 dmar0 block interrupt ivg7 2 0 iar0 imask0, isr0, iwr0 dmar1 block interrupt ivg7 3 0 iar0 imask0, isr0, iwr0 dmar0 overflow error ivg7 4 0 iar0 imask0, isr0, iwr0 dmar1 overflow error ivg7 5 0 iar0 imask0, isr0, iwr0 ppi error ivg7 6 0 iar0 imask0, isr0, iwr0 mac status ivg7 7 0 iar0 imask0, isr0, iwr0 sport0 status ivg7 8 0 iar1 imask0, isr0, iwr0 sport1 status ivg7 9 0 iar1 imask0, isr0, iwr0 reserved ivg7 10 0 iar1 imask0, isr0, iwr0 reserved ivg7 11 0 iar1 imask0, isr0, iwr0 uart0 status ivg7 12 0 iar1 imask0, isr0, iwr0 uart1 status ivg7 13 0 iar1 imask0, isr0, iwr0 rtc ivg8 14 1 iar1 imask0, isr0, iwr0 dma channel 0 (ppi/nfc) ivg8 15 1 iar1 imask0, isr0, iwr0 dma channel 3 (sport0 rx) ivg9 16 2 iar2 imask0, isr0, iwr0 dma channel 4 (sport0 tx) ivg9 17 2 iar2 imask0, isr0, iwr0 dma channel 5 (sport1 rx) ivg9 18 2 iar2 imask0, isr0, iwr0 dma channel 6 (sport1 tx) ivg9 19 2 iar2 imask0, isr0, iwr0 twi ivg10 20 3 iar2 imask0, isr0, iwr0 dma channel 7 (spi) ivg10 21 3 iar2 imask0, isr0, iwr0 dma channel 8 (uart0 rx) ivg10 22 3 iar2 imask0, isr0, iwr0 dma channel 9 (uart0 tx) ivg10 23 3 iar2 imask0, isr0, iwr0 dma channel 10 (uart1 rx) ivg10 24 3 iar3 imask0, isr0, iwr0 dma channel 11 (uart1 tx) ivg10 25 3 iar3 imask0, isr0, iwr0
rev. d | page 8 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 event control the processor provides a very fl exible mechanism to control the processing of events. in the ce c, three registers are used to coordinate and control events. ea ch register is 16 bits wide. ? cec interrupt latch register (ilat) indicates when events have been latched. th e appropriate bit is set when the processor has latched the event and cleared when the event has been accepted into the system. this register is updated automatically by the controller, but it may be writ- ten only when its corresponding imask bit is cleared. ? cec interrupt mask regist er (imask) controls the masking and unmasking of indivi dual events. when a bit is set in the imask register, that event is unmasked and is processed by the cec when a sserted. a cleared bit in the imask register masks the event, preventing the processor from servicing the event even though the event may be latched in the ilat register. th is register ma y be read or written while in supervisor mode. (note that general- purpose interrupts can be gl obally enabled and disabled with the sti and cli instructions, respectively.) ? cec interrupt pending register (ipend) the ipend register keeps track of all ne sted events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but may be read while in supervisor mode. the sic allows further control of event processing by providing three pairs of 32-bit interrupt co ntrol and status registers. each register contains a bi t corresponding to each of the peripheral interrupt events shown in table 3 on page 7 . ? sic interrupt mask register s (sic_imaskx) control the masking and unmasking of each peripheral interrupt event. when a bit is set in these registers, that peripheral event is otp memory interrupt ivg11 26 4 iar3 imask0, isr0, iwr0 gp counter ivg11 27 4 iar3 imask0, isr0, iwr0 dma channel 1 (mac rx/hostdp) ivg11 28 4 iar3 imask0, isr0, iwr0 port h interrupt a ivg11 29 4 iar3 imask0, isr0, iwr0 dma channel 2 (mac tx/nfc) ivg11 30 4 iar3 imask0, isr0, iwr0 port h interrupt b ivg11 31 4 iar3 imask0, isr0, iwr0 timer 0 ivg12 32 5 iar4 imask1, isr1, iwr1 timer 1 ivg12 33 5 iar4 imask1, isr1, iwr1 timer 2 ivg12 34 5 iar4 imask1, isr1, iwr1 timer 3 ivg12 35 5 iar4 imask1, isr1, iwr1 timer 4 ivg12 36 5 iar4 imask1, isr1, iwr1 timer 5 ivg12 37 5 iar4 imask1, isr1, iwr1 timer 6 ivg12 38 5 iar4 imask1, isr1, iwr1 timer 7 ivg12 39 5 iar4 imask1, isr1, iwr1 port g interrupt a ivg12 40 5 iar5 imask1, isr1, iwr1 port g interrupt b ivg12 41 5 iar5 imask1, isr1, iwr1 mdma stream 0 ivg13 42 6 iar5 imask1, isr1, iwr1 mdma stream 1 ivg13 43 6 iar5 imask1, isr1, iwr1 software watchdog timer ivg13 44 6 iar5 imask1, isr1, iwr1 port f interrupt a ivg13 45 6 iar5 imask1, isr1, iwr1 port f interrupt b ivg13 46 6 iar5 imask1, isr1, iwr1 spi status ivg7 47 0 iar5 imask1, isr1, iwr1 nfc status ivg7 48 0 iar6 imask1, isr1, iwr1 hostdp status ivg7 49 0 iar6 imask1, isr1, iwr1 host read done ivg7 50 0 iar6 imask1, isr1, iwr1 reserved ivg10 51 3 iar6 imask1, isr1, iwr1 usb_int0 interrupt ivg10 52 3 iar6 imask1, isr1, iwr1 usb_int1 interrupt ivg10 53 3 iar6 imask1, isr1, iwr1 usb_int2 interrupt ivg10 54 3 iar6 imask1, isr1, iwr1 usb_dmaint interrupt ivg10 55 3 iar6 imask1, isr1, iwr1 table 3. system interrupt controller (sic) (continued) peripheral interrupt event general purpose interrupt (at reset )peripheral interrupt id default core interrupt id sic registers
rev. d | page 9 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 unmasked and is processed by the system when asserted. a cleared bit in the register masks the peripheral event, pre- venting the processor from servicing the event. ? sic interrupt status registers (sic_isrx) as multiple peripherals can be ma pped to a single event, these registers allow the software to determ ine which peripheral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, and a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wakeup enable registers (sic_iwrx) by enabling the correspo nding bit in these registers, a periph- eral can be configured to wake up the processor, should the core be idled or in sleep mode when the event is generated. for more information see dynamic power management on page 14 . because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. the ipend register contents are monitore d by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requ ires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec recogn izes and queues the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend ou tput asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. dma controllers the processor has multiple, in dependent dma channels that support automated data transfers with minimal overhead for the processor core. dma transfers can occur between the processor's internal memories and any of its dma-capable peripherals. addition ally, dma transfers ca n be accomplished between any of the dma-capabl e peripherals and external devices connected to the external memory interfaces, including the sdram controller and the asynchronous memory control- ler. dma-capable peripherals in clude the ethernet mac, nfc, hostdp, usb, sports, spi port, uarts, and ppi. each indi- vidual dma-capable peripheral has at least one dedicated dma channel. the processor dma controller supports both one-dimensional (1-d) and two-dimensional (2-d) dma transfers. dma trans- fer initialization can be implemen ted from registers or from sets of parameters called descriptor blocks. the 2-d dma capability suppor ts arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to 3 2k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video applications where data can be de- interleaved on the fly. examples of dma types support ed by the processor dma con- troller include: ? a single, linear buffer th at stops upon completion. ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer. ? 1-d or 2-d dma using a li nked list of descriptors. ? 2-d dma using an array of descriptors, specifying only the base dma address with in a common page. in addition to the dedicated peripheral dma channels, there are two memory dma channels provided for transfers between the various memories of the proce ssor system. this enables trans- fers of blocks of data between any of the memoriesincluding external sdram, rom, sram, and flash memorywith mini- mal processor intervention. me mory dma transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism. the processor also has an exte rnal dma controller capability via dual external dma request pi ns when used in conjunction with the external bus interface unit (ebiu). this functionality can be used when a high speed in terface is required for external fifos and high bandwidth communications peripherals such as usb 2.0. it allows control of th e number of data transfers for memory dma. the number of transfers per edge is program- mable. this feature can be programmed to allow memory dma to have an increased priority on the external bus relative to the core. host dma port the host port interface allows an external host to be a dma master to transfer data in and ou t of the device. the host device masters the transactions and th e blackfin processor is the dma slave. the host port is enabled through the pab interface. once enabled, the dma is controlled by the external host, which can then program the dma to send/rec eive data to any valid inter- nal or external memory location. the host port interface contro ller has the following features. ? allows external master to co nfigure dma read/write data transfers and read port status. ? uses asynchronous memory protocol for external interface. ? 8-/16-bit external data interface to host device. ? half duplex operation. ? little-/big-endian data transfer. ? acknowledge mode allows flow control on host transactions. ? interrupt mode guarantees a burst of fifo depth host transactions. real-time clock the real-time clock (rtc) provides a robust set of digital watch features, including current time , stopwatch, and alarm. the rtc is clocked by a 32.768 khz crystal external to the blackfin processor. connect rtc pins rt xi and rtxo with external
rev. d | page 10 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 components as shown in figure 4 . the rtc peripheral has dedicated power supply pins so that it can remain powered up and clocke d even when the rest of the processor is in a low power stat e. the rtc provides several pro- grammable interrupt options, in cluding interrupt per second, minute, hour, or day clock ticks, interrupt on programmable stopwatch countdown, or interrupt at a programmed alarm time. the 32.768 khz input clock frequency is divided down to a 1 hz signal by a prescaler. the counter function of the timer consists of four counters: a 60-second co unter, a 60-minute counter, a 24-hour counter, and an 32,768-day counter. when enabled, the alarm function generates an interrupt when the output of the timer matches the programmed value in the alarm control register. there are two alarms: the first alarm is for a time of day. the second alarm is for a day and time of that day. the stopwatch function counts down from a programmed value, with one-second resolu tion. when the stopwatch is enabled and the counter underflows, an interrupt is generated. like the other peripherals, the rtc can wake up the processor from sleep mode upon generati on of any rtc wake-up event. additionally, an rtc wakeup ev ent can wake up the processor from deep sleep mode or cause a transition from the hibernate state. watchdog timer the processor includes a 32-bit timer that can be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (nmi), or general-pu rpose interrupt, if the timer expires before being reset by so ftware. the programmer initial- izes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the pro- grammed value. this protects the system from remaining in an unknown state where software, wh ich would normally reset the timer, has stopped running due to an external noise condition or software error. if configured to gene rate a hardware reset, the watchdog timer resets both the core and the proc essor peripherals. after a reset, software can determine if the wa tchdog was the source of the hardware reset by interrogating a status bit in the watchdog timer control register. the timer is clocked by the syst em clock (sclk), at a maximum frequency of f sclk . timers there are nine general-purpose programmable timer units in the processors. eight timers have an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and peri ods of external events. these timers can be synchronized to an external clock input to the sev- eral other associated pf pins, an external clock input to the ppi_clk input pin, or to the internal sclk. the timer units can be used in conjunction with the two uarts to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrupt s to the processor core provid- ing periodic events for synchron ization, either to the system clock or to a count of external signals. in addition to the eight genera l-purpose progra mmable timers, a ninth timer is also provided. th is extra timer is clocked by the internal processor clock and is ty pically used as a system tick clock for generation of operatin g system periodic interrupts. up/down counter and thumbwheel interface a 32-bit up/down counter is provided that can sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumb wheels. the counter can also operate in general-purpose up/down count modes. then, count direction is either controlled by a level-sensitive input pin or by two edge detectors. a third input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins have a pr ogrammable debouncing circuit. an internal signal forwarded to the timer unit enables one timer to measure the intervals between count events. boundary regis- ters enable auto-zero operation or simple system warning by interrupts when programmable count values are exceeded. serial ports the processors incorporate two dual-channel synchronous serial ports (sport0 and sport1) for serial and multiproces- sor communications. the spor ts support the following features: ?i 2 s capable operation. figure 4. external components for rtc rtxo c1 c2 x1 suggested components: x1 = ecliptek ec38j (through-hole package) or epson mc405 12 pf load (surface-mount package) c1 = 22 pf c2 = 22 pf r1 = 10 m : note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. c1 and c2 specifications assume board trace capacitance of 3 pf. rtxi r1
rev. d | page 11 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 ? bidirectional operation each sport has two sets of independent transmit and receive pins, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports each port has a data register for transfe rring data words to and from other processor components and shift registers for shifting data in and out of the data registers. ? clocking each transmit and receive port can either use an external serial clock or ge nerate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 to 32 bits in length, tr ansferred most-significant-bit first or least-significant-bit first. ? framing each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. ? companding in hardware each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with sing le-cycle overhead each sport can automatically rece ive and transmit multiple buffers of memory data. the processor can link or chain sequences of dma transfers between a sport and memory. ? interrupts each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer, or buffers, through dma. ? multichannel capability each sport supports 128 channels out of a 1024-channe l window and is compatible with the h.100, h.110, mvip-9 0, and hmvip standards. serial peripheral interface (spi) port the processors have an spi-compatible port that enables the processor to communicate with multiple spi-compatible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosi, and master input- slave output, miso) and a clock pin (serial clock, sck). an spi chip select input pin (spiss ) lets other spi devices select the processor, and seven spi chip select output pins (spisel7C1 ) let the processor select other spi de vices. the spi select pins are reconfigured general-purpose i/ o pins. using these pins, the spi port provides a full-duplex, synchronous serial interface, which supports both master/s lave modes and multimaster environments. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has an integrated dma channel, configurable to support transmit or receive data streams. the spis dma channel can only serv ice unidirectional accesses at any given time. the spi ports clock rate is calculated as: where the 16-bit spi_baud register contains a value of 2 to 65,535. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on its two serial data lines. the serial clock line sy nchronizes the shifting and sam- pling of data on the two serial data lines. uart ports the processors provide two full- duplex universal asynchronous receiver/transmitter (uart) ports, which are fully compatible with pc-standard uarts. each uart port provides a simpli- fied uart interface to other peripherals or hosts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. a uart port includes suppo rt for five to eight data bits, one or two stop bits, and none, even, or odd parity. each uart port supports two modes of operation: ? pio (programmed i/o) the processor sends or receives data by writing or reading i/o mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) the dma controller transfers both transmit and re ceive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. each uart port's baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk /16) bits per second. ? supporting data formats from seven to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. the uart ports clock rate is calculated as: where the 16-bit uart_divisor comes from the uart_dlh (most significant 8 bits) and uart_dll (least significant 8 bits) registers. in conjunction with the general- purpose timer functions, auto- baud detection is supported. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. spi clock rate f sclk 2 spi_baud ? ----------------------------------- - = uart clock rate f sclk 16 uart_divisor ? ----------------------------------------------- =
rev. d | page 12 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 twi controller interface the processors include a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi is co mpatible with the widely used i 2 c ? bus standard. the twi module offers the capa bilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitration. the twi interface utilizes two pins for transferring clock (scl) and data (sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compatible with 5 v logic levels. additionally, the twi module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. 10/100 ethernet mac the adsp-bf526 and adsp-bf527 processors offer the capa- bility to directly connect to a network by way of an embedded fast ethernet media access co ntroller (mac) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 ethernet ma c peripheral on the proces- sor is fully compliant to the ieee 802.3-2002 st andard and it provides programmable features designed to minimize supervi- sion, bus use, or message processi ng by the rest of the processor system. some standard features are: ? support of mii and rmii pr otocols for external phys. ? full duplex and half duplex modes. ? data framing and encapsulation: generation and detection of preamble, length padding, and fcs. ? media access management (in half-duplex operation): col- lision and contention handling, including control of retransmission of collision fr ames and of back-off timing. ? flow control (in full-duplex operation): generation and detection of pause frames. ? station management: generation of mdc/mdio frames for read-write access to phy registers. ? operating range for active and sleep operating modes, see table 58 on page 68 and table 59 on page 68 . ? internal loopback from tx to rx. some advanced features are: ? buffered crystal output to ex ternal phy for support of a single crystal system. ? automatic checksum computat ion of ip header and ip payload fields of rx frames. ? independent 32-bit descriptor-driven rx and tx dma channels. ? frame status delivery to memory via dma, including frame completion semaphores, for efficient buffer queue management in software. ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations. ? convenient frame alignment modes support even 32-bit alignment of encapsulated rx or tx ip packet data in mem- ory after the 14-byte mac header. ? programmable ethernet even t interrupt supports any com- bination of: ? any selected rx or tx frame status conditions. ? phy interrupt condition. ? wake-up frame detected. ? any selected mac management counter(s) at half- full. ? dma descriptor error. ? 47 mac management statistics counters with selectable clear-on-read behavior and programmable interrupts on half maximum value. ? programmable rx address fi lters, including a 64-bin address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, uni- cast, control, an d damaged frames. ? advanced power management supporting unattended transfer of rx and tx frames and status to/from external memory via dma during low power sleep mode. ? system wakeup from sleep operating mode upon magic packet or any of four user-d efinable wakeup frame filters. ? support for 802.3q tagged vlan frames. ? programmable mdc clock rate and preamble suppression. ? in rmii operation, seven unused pins may be configured as gpio pins for other purposes. ports because of the rich set of periph erals, the processor groups the many peripheral signals to four portsport f, port g, port h, and port j. most of the associated pins are shared by multiple signals. the ports function as multiplexer controls. general-purpose i/o (gpio) the processor has 48 bidirectional, general-purpose i/o (gpio) pins allocated across three sepa rate gpio modulesportfio, portgio, and porthio, associated with port f, port g, and port h, respectively. port j does not provide gpio functional- ity. each gpio-capable pin shares functionality with other processor peripherals via a mult iplexing scheme; however, the gpio functionality is the default state of the device upon power-up. neither gpio output nor input drivers are active by default.
rev. d | page 13 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 each general-purpose port pin can be individually controlled by manipulation of the port control, status, and interrupt registers: ? gpio direction control register specifies the direction of each individual gpio pin as input or output. ? gpio control and status registers the processor employs a write one to modify mechanism that allows any combination of individual gpio pins to be modified in a single instruction, without a ffecting the level of any other gpio pins. four control regi sters are provided. one regis- ter is written in order to set pin values, one register is written in order to clear pin va lues, one register is written in order to toggle pin values, and one register is written in order to specify a pin value. reading the gpio status regis- ter allows software to interrogate the sense of the pins. ? gpio interrupt mask registers the two gpio interrupt mask registers allow each indi vidual gpio pin to function as an interrupt to the processor. similar to the two gpio control registers that are used to set and clear individual pin values, one gpio interrupt mask register sets bits to enable interrupt function, and the other gpio interrupt mask register clears bits to disable interrupt function. gpio pins defined as inputs ca n be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers the two gpio inter- rupt sensitivity registers specif y whether individual pins are level- or edge-sensitive an d specifyif edge-sensitive whether just the rising edge or both the rising and falling edges of the signal are signific ant. one register selects the type of sensitivity, and one re gister selects which edges are significant for edge-sensitivity. parallel peripheral interface (ppi) the processor provides a parallel peripheral interface (ppi) that can connect directly to parallel analog-to-di gital and digital-to- analog converters, video encoders and decoders, and other gen- eral-purpose peripherals. the ppi consists of a dedicated input clock pin, up to three frame synchronization pins, and up to 16 data pins. the input clock supports parallel data rates up to half the system clock rate, and the synchronization signals can be configured as either inputs or outputs. the ppi supports a variety of general-purpose and itu-r 656 modes of operation. in general- purpose mode, the ppi provides half-duplex, bidirectional data tr ansfer with up to 16 bits of data. up to three frame synchr onization signals are also pro- vided. in itu-r 656 mode, th e ppi provides half-duplex bidirectional transfer of 8- or 10-bit video data. additionally, on-chip decode of embedded start-of-line (sol) and start-of- field (sof) preamble packets is supported. general-purpose mode descriptions the general-purpose modes of th e ppi are intended to suit a wide variety of data capture and transmission applications. three distinct submodes are supported: 1. input mode frame syncs an d data are inputs into the ppi. 2. frame capture mode frame syncs are outputs from the ppi, but data are inputs. 3. output mode frame syncs and data are outputs from the ppi. input mode input mode is intended for adc applications, as well as video communication with hardware sign aling. in its simplest form, ppi_fs1 is an external frame sync input that controls when to read data. the ppi_delay mmr allows for a delay (in ppi_- clk cycles) between reception of this frame sync and the initiation of data reads. the number of input data samples is user programmable and defined by the contents of the ppi_count register. the ppi supports 8-bit and 10-bit through 16-bit data, programm able in the ppi_control register. frame capture mode frame capture mode allows the video source(s) to act as a slave (for frame capture for example) . the adsp-bf52x processors control when to read from the video source(s). ppi_fs1 is an hsync output, and ppi_fs2 is a vsync output. output mode output mode is used for transmitting video or other data with up to three output frame syncs. typically, a single frame sync is appropriate for data converter applications, whereas two or three frame syncs could be used for sending video with hard- ware signaling. itu-r 656 mode descriptions the itu-r 656 modes of the ppi are intended to suit a wide variety of video capture, proce ssing, and transmission applica- tions. three distinct submodes are supported: 1. active video only mode 2. vertical blanking only mode 3. entire field mode active video mode active video only mode is used when only the active video por- tion of a field is of interest and not any of the blanking intervals. the ppi does not read in any da ta between the end of active video (eav) and start of active video (sav) preamble symbols, or any data present during the vertical blanking intervals. in this mode, the control byte sequence s are not stored to memory; they are filtered by the ppi. afte r synchronizing to the start of field 1, the ppi ignores incoming samples until it sees an sav code. the user specifies the number of active video lines per frame (in ppi_count register). vertical blanking interval mode in this mode, the ppi only transf ers vertical blanking interval (vbi) data.
rev. d | page 14 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 entire field mode in this mode, the entire incoming bit stream is read in through the ppi. this includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and ver- tical blanking intervals. data transfer starts immediately after synchronization to field 1. data is transferred to or from the synchronous channels through eight dma engines that work autonomously from the processor core. usb on-the-go dual-role device controller the usb otg dual-role device controller (usbdrc) provides a low-cost connectivity solution for consumer mobile devices such as cell phones, digital st ill cameras, and mp3 players, allowing these devices to transf er data using a point-to-point usb connection without the need for a pc host. the usbdrc module can operate in a tradit ional usb peripheral-only mode as well as the host mode presented in the on-the-go (otg) supplement to the usb 2.0 specific ation. in host mode, the usb module supports transfers at hi gh speed (480 mbps), full speed (12 mbps), and low speed (1.5 mbps) rates. peripheral-only mode supports the high- and full-speed transfer rates. the usb clock (usb_xi) is prov ided through a dedicated exter- nal crystal or crystal oscillator. see universal serial bus (usb) on-the-goreceive and transmit timing on page 60 for related timing requirements. if using a crystal to provide the usb clock, use a parallel-reso nant, fundamental mode, micro- processor-grade crystal. the usb on-the-go dual-role device controller includes a phase locked loop with programmable mu ltipliers to generate the nec- essary internal clocking frequenc y for usb. the multiplier value should be programmed based on the usb_xi frequency to achieve the necessary 480 mhz internal clock for usb high speed operation. for example, for a usb_xi crystal frequency of 24 mhz, the usb_pllosc_ctrl register should be pro- grammed with a multiplier value of 20 to generate a 480 mhz internal clock. code security with lockbox secure technology a security system consisting of a blend of hardware and soft- ware provides customers with a flexible and rich set of code security features with lockbox tm secure technology. key fea- tures include: ?otp memory ? unique chip id ? code authentication ? secure mode of operation the security scheme is based upon the concept of authentica- tion of digital signatures usin g standards-based algorithms and provides a secure processing en vironment in wh ich to execute code and protect assets. see lockbox secure technology dis- claimer on page 22 . dynamic power management the processor provides five oper ating modes, each with a differ- ent performance/power profile. in addition, dynamic power management provides the control functions to dynamically alter the processor core supply voltage, further reducing power dissi- pation. when configured for a 0 v core supply voltage, the processor enters the hibernate stat e. control of clocking to each of the processor peripherals al so reduces power consumption. see table 4 for a summary of the powe r settings for each mode. full-on operating modemaximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the power-up default execut ion state in which maximum per- formance can be achieved. the processor core and all enabled peripherals run at full speed. active operating modemoderate dynamic power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processors core clock (cclk) and system clock (sclk) run at the input clock (clkin) frequency. dma access is available to appropriately configured l1 memories. in the active mode, it is possible to disable the control input to the pll by setting the pll_off bit in the pll control register. this register can be accessed with a user-callable routine in the on-chip rom called bfrom_syscontrol(). if disabled, the pll control input must be re-enabled before transitioning to the full-on or sleep modes. for more information about pll controls, see the dynamic power management chapter in the adsp-bf52x blackfin pro- cessor hardware reference. sleep operating modehigh dynamic power savings the sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (cclk). the pll and system clock (sclk), however, continue to operate in this mode. typi- cally, an external event or rtc ac tivity wakes up the processor. when in the sleep mode, asserting a wakeup enabled in the sic_iwrx registers causes the pr ocessor to sense the value of the bypass bit in the pll control register (pll_ctl). if bypass is disabled, the processo r transitions to the full-on mode. if bypass is enabled, th e processor transitions to the active mode. table 4. power settings mode/state pll pll bypassed core clock (cclk) system clock (sclk) core power full-on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled disabled enabled on deep sleep disabled disabled disabled on hibernate disabled disabled disabled off
rev. d | page 15 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 system dma access to l1 me mory is not supported in sleep mode. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes dynamic power savings by dis- abling the clocks to the processor core (cclk) and to all synchronous peripherals (sclk) . asynchronous peripherals, such as the rtc, may still be ru nning but cannot access internal resources or external memory. this powered-down mode can only be exited by assertion of the reset interrupt (reset ) or by an asynchronous interrupt generated by the rtc. when in deep sleep mode, an rtc asynchronous interrupt causes the proces- sor to transition to the acti ve mode. assertion of reset while in deep sleep mode causes the pr ocessor to transition to the full on mode. hibernate statemaximum static power savings the hibernate state maximizes stat ic power savings by disabling the voltage and clocks to the proc essor core (cclk) and to all of the synchronous peripherals (scl k). the internal voltage regu- lator (adsp-bf523/adsp-bf525/ adsp-bf527 only) for the processor can be shut off by writ ing b#00 to the freq bits of the vr_ctl register, using the bfro m_syscontrol() function. this setting sets the internal power supply voltage (v ddint ) to 0 v to provide the lowest static power dissipation. any critical infor- mation stored internally (for example, memory contents, register contents, and other information) must be written to a non volatile storage device prior to removing power if the pro- cessor state is to be preserved. writing b#00 to the freq bits also causes ext_wake0 and ext_wake1 to transition low, which can be used to signal an external voltage regulator to shut down. since v ddext and v ddmem can still be supplied in this mode, all of the external pins three-state, unless otherwise specified. this allows other devices that may be connected to the processor to still have power applied without drawing unwanted current. the ethernet or usb modules can wake up the internal supply regulator (adsp-bf525 and adsp -bf527 only) or signal an external regulator to wake up using ext_wake0 or ext_wake1. if pg15 does not connect as a phyint signal to an external phy device, pg15 ca n be pulled low by any other device to wake the processor up. the processor can also be woken up by a real-time clock wakeup event or by asserting the reset pin. all hibernate wake-up events initiate the hardware reset sequence. individual sour ces are enabled by the vr_ctl register. the ext_wakex signals are provided to indicate the occurrence of wake-up events. as long as v ddext is applied, the vr_ctl register maintains its state during hibernation. all other internal registers and memo- ries, however, lose their content in the hibernate state. state variables may be held in ex ternal sram or sdram. the sckelow bit in the vr_ctl register controls whether or not sdram operates in self-refresh mo de, which allows it to retain its content while the processor is in hibernate and through the subsequent reset sequence. power savings as shown in table 5 , the processor supports six different power domains, which maximizes flexibility while maintaining com- pliance with industry standards and conventions. by isolating the internal logic of the proces sor into its own power domain, separate from the rtc and othe r i/o, the processor can take advantage of dynamic power management without affecting the rtc or other i/o devices. there are no sequencing require- ments for the various power doma ins, but all do mains must be powered according to the appropriate specifications table for processor operating conditions; ev en if the feature/peripheral is not used. the dynamic power management feature of the processor allows both the processors input voltage (v ddint ) and clock fre- quency (f cclk ) to be dynamically controlled. the power dissipated by a processo r is largely a function of its clock frequency and the square of the operating voltage. for example, reducing the clock freq uency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. further, these power sa vings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic, as shown in the following equations. where the variables in the equations are: f cclknom is the nominal core clock frequency f cclkred is the reduced core clock frequency v ddintnom is the nominal internal supply voltage v ddintred is the reduced internal supply voltage t nom is the duration running at f cclknom t red is the duration running at f cclkred table 5. power domains power domain v dd range all internal logic, except rtc, memory, usb, otp v ddint rtc internal logic and crystal i/o v ddrtc memory logic v ddmem usb phy logic v ddusb otp logic v ddotp all other i/o v ddext power savings factor f cclkred f cclknom -------------------------- v ddintred v ddintnom ------------------------------- - ?? ?? 2 ? t red t nom -------------- - ? ? ? ? ? = % power savings 1 po wer savings factor ? ?? 100% ? =
rev. d | page 16 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 adsp-bf523/adsp-bf525/adsp-bf527 voltage regulation the adsp-bf523/adsp-bf525/ad sp-bf527 provides an on- chip voltage regulator that can generate processor core voltage levels from an external supply. figure 5 shows the typical exter- nal components required to complete the power management system. the regulator controls the intern al logic voltage levels and is programmable with the voltag e regulator control register (vr_ctl) in increments of 50 mv. this register can be accessed using the bfrom_syscontrol() function in the on-chip rom. to reduce standby power co nsumption, the internal volt- age regulator can be programm ed to remove power to the processor core while keeping i/ o power supplied. while in the hibernate state, all external supplies (v ddext , v ddmem , v ddusb , v ddotp ) can still be applied, eliminating the need for external buffers. v ddrtc must be applied at all times for correct hibernate operation. the voltage regulator can be activated from this power-down state either through an rtc wakeup, a usb wake- up, an ethernet wake-up, or by asserting the reset pin, each of which then initiates a boot sequence. the regulator can also be disabled and bypassed at the users discretion. the voltage regulator has two modes set by the vr sel pinthe normal pulse width control of an external fet and the external supply mode which can signal a power down during hibernate to an external regulator. set vr sel to v ddext to use an external regulator or set vr sel to gnd to use the internal regulator. in the external mode vr out becomes ext_wake1. if the internal regulator is used, ext_wake0 can control other power sources in the system during th e hibernate state. both signals are high-true for power-up and may be connected directly to the low-true shutdown input of many common regulators. the mode of the ss/pg (soft start/power good ) signal also changes according to the state of vr sel . when using an internal regula- tor, the ss/pg pin is soft start, and when using an external regulator, it is power good. the soft start feature is recom- mended to reduce the inrush currents and to reduce v ddint voltage overshoot when coming out of hibernate or changing voltage levels. the power good (pg ) input signal allows the processor to start only after th e internal voltage has reached a chosen level. in this way, the startup time of the external regulator is detected after hibernation. for a complete description of soft start and power good functionality, refer to the adsp-bf52x blackfin proc essor hardware reference . adsp-bf522/adsp-bf524/adsp-bf526 voltage regulation the adsp-bf522/adsp-bf524/adsp-bf526 processor requires an external voltag e regulator to power the v ddint domain. to reduce standby powe r consumption, the external voltage regulator can be sign aled through ext_wake0 or ext_wake1 to remove power from the processor core. these identical signals are high-true for power-up and may be con- nected directly to the low-tr ue shut down input of many common regulators. while in the hibernate state, all external supplies (v ddext , v ddmem , v ddusb , v ddotp ) can still be applied, eliminating the need for external buffers. v ddrtc must be applied at all times for correct hi bernate operation. the external voltage regulator can be activated from this power down state either through an rtc wakeup , a usb wakeup, an ethernet wakeup, or by asserting the reset pin, each of which then initi- ates a boot sequence. ext_wake0 or ext_wake1 indicate a wakeup to the external voltage regulator. the power good (pg ) input signal allows the processor to start only after the internal voltage has reached a chosen level. in this way, the startup time of the external regulator is de tected after hibernation. for a complete description of the powe r good functionality, refer to the adsp-bf52x blackfin proc essor hardware reference . clock signals the processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the proce ssor includes an on-chip oscilla- tor circuit, an external crystal may be used. for fundamental frequency operation, use the circuit shown in figure 6 . a parallel-resonant, fundamenta l frequency, microprocessor- grade crystal is connected across the clkin and xtal pins. the on-chip resistance between clkin and the xtal pin is in the 500 k range. further parallel resistors are ty pically not rec- ommended. the two capacitors and the series resistor shown in figure 6 fine tune phase and amplitude of the sine frequency. the capacitor and resist or values shown in figure 6 are typical values only. the capacitor values are dependent upon the crystal manufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level figure 5. adsp-bf523/adsp-bf525/ads p-bf527 voltage regulator circuit v ddext (low-inductance) v ddint 100f vr out ext_wake1 gnd short and low- inductance wire v ddext ++ + 100f 100f 10 f low esr 100nf set of decoupling capacitors fds9431a zhcs1000 2.25v to 3.6v input voltage range note: designer should minimize trace length to fds9431a. 10h vr sel ss/ pg see h/w reference, system design chapter, to determine value
rev. d | page 17 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 specified by the crystal manufactur er. the user should verify the customized values based on care ful investigations on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone by ad ding a tuned inductor circuit as shown in figure 6 . a design procedure fo r third-overtone oper- ation is discussed in detail in application note (ee-168) using third overtone crystals with the adsp-218x dsp on the analog devices website ( www.analog.com )use site search on ee-168. the clkbuf pin is an output pin, which is a buffered version of the input clock. this pin is particularly useful in ethernet applications to limit the number of required clock sources in the system. in this type of application, a single 25 mhz or 50 mhz crystal may be applied directly to the processor. the 25 mhz or 50 mhz output of clkbuf can then be connected to an exter- nal ethernet mii or rmii phy device. if, instead of a crystal, an external oscillator is used at clkin, clkbuf will not have the 40/60 duty cycle required by some devices. the clkbuf output is active by default and can be disabled for power savings rea- sons using the vr_ctl register. the blackfin core runs at a different clock rate than the on-chip peripherals. as shown in figure 7 , the core clock (cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a programm able multiplication factor (bounded by specified minimum and maximum vco frequen- cies). the default multiplier ca n be modified by a software instruction sequence. this sequence is managed by the bfrom_syscontrol() function in the on-chip rom. on-the-fly cclk and sclk frequency changes can be applied by using the bfrom_syscontrol() function in the on-chip rom. the maximum allowed cclk and sclk rates depend on the applied voltages v ddint , v ddext , and v ddmem ; the vco is always permitted to run up to the frequency specified by the parts maximum instruction rate. the cl kout pin reflects the sclk frequency to the off-chip world. it is part of the sdram inter- face, but it functions as a refe rence signal in other timing specifications as well. while active by default, it can be disabled using the ebiu_sdgctl and ebiu_amgctl registers. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 6 illustrates typical system clock ratios. note that the divisor ratio must be chosen to limit the system clock frequency to its maximum of f sclk . the ssel value can be dynamically changed without any pll lock latencies by writing the appropriate values to the pll divisor register (pll_div) using the bfrom_syscontrol() function in the on-chip rom. the core clock (cclk) freque ncy can also be dynamically changed by means of the csel1C0 bits of the pll_div register. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 7 . this programmable core cloc k capability is useful for fast core frequency modifications. figure 6. external crystal connections clkin clkout xtal en clkbuf to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18 pf should be treated as a maximum, and the suggested resistor value should be reduced to 0 . 18 pf * en 18 pf * 330 * blackfin 560 figure 7. frequency mo dification methods table 6. example system clock ratios signal name ssel3C0 divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50 table 7. core clock ratios signal name csel1C0 divider ratio vco/cclk example frequency ratios (mhz) vco cclk 00 1:1 300 300 01 2:1 300 150 10 4:1 500 125 11 8:1 200 25 pll 5 u to 64 u 1to15 1,2,4,8 vco clkin fine adjustment requires pll sequencing coarse adjustment on-the-fly cclk sclk sclk d cclk
rev. d | page 18 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 the maximum cclk frequency not only depends on the part's maximum instruction rate (see page 88 ). this frequency also depends on the applied v ddint voltage. see table 12 and table 15 for details. the maximal system clock rate (sclk) depends on the chip package and the applied v ddint , v ddext , and v ddmem voltages (see table 14 and table 17 ). booting modes the processor has several mechanisms (listed in table 8 ) for automatically loading internal and external memory after a reset. the boot mode is defined by four bmode input pins dedicated to this purpose. ther e are two catego ries of boot modes. in master boot modes the processor actively loads data from parallel or serial memories . in slave boot modes the pro- cessor receives data from external host devices. the boot modes listed in table 8 provide a number of mecha- nisms for automatically loading the proce ssors internal and external memories after a reset. by default, all boot modes use the slowest meaningful configuration settings. default settings can be altered via the initialization code feature at boot time or by proper otp programming at pre-boot time. the bmode pins of the reset configuration register, sampled during power- on resets and software-initiated resets, implement the modes shown in table 8 . ? idle/no boot mode (bmode = 0x0) in this mode, the processor goes into idle. the idle boot mode helps recover from illegal operat ing modes, such as when the otp mem- ory has been misconfigured. ? boot from 8-bit or 16-bi t external flash memory (bmode = 0x1) in this mode, the boot kernel loads the first block header from ad dress 0x2000 0000, and (depend- ing on instructions contained in the header) the boot kernel performs an 8- or 16-bit boot or starts program exe- cution at the address provided by the header. by default, all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle r/w access times, 4-cycle setup). the ardy is not enabled by default, but it can be enabled through otp programming. similarly, all interface behav- ior and timings can be customized through otp programming. this includes activation of burst-mode or page-mode operation. in this mode, all asynchronous interface signals are enabled at the port muxing level. ? boot from 16-bit asynchronous fifo (bmode = 0x2) in this mode, the boot kernel starts booting from address 0x2030 0000. every 16-bit word th at the boot kernel has to read from the fifo must be requested by placing a low pulse on the dmar1 pin. ? boot from serial spi memory, eeprom or flash (bmode = 0x3) 8-, 16-, 24- , or 32-bit addressable devices are supported. the processor uses the pg1 gpio pin to select a single spi eeprom/flash device and sub- mits a read command and succ essive address bytes (0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device is detected. pull-up resistors ar e required on the spisel1 and miso pins. by default, a value of 0x85 is written to the spi_baud register. ? boot from spi host device (bmode = 0x4) the proces- sor operates in spi slave mode and is configured to receive the bytes of the ldr file from an spi host (master) agent. the hwait signal must be inte rrogated by the host before every transmitted byte. a pull-up resistor is required on the spiss input. a pull-down on the serial clock (sck) may improve signal quality and booting robustness. ? boot from serial twi memory, eeprom/flash (bmode = 0x5) the processor operates in master mode and selects the twi slave connected to the twi with the unique id 0xa0. the processor submits successi ve read commands to the memory device starting at internal address 0x0000 and begins clocking data into th e processor. the twi memory device should comply with the philips i 2 c ? bus specifica- tion version 2.1 and should be able to auto-increment its internal address counter such that the contents of the memory device can be read sequentially. by default, a prescale value of 0xa and a twi_clkdiv value of 0x0811 are used. unless alte red by otp settings, an i 2 c memory that takes two addr ess bytes is assumed. the development tools ensure that data booted to memories that cannot be accessed by the blackfin core is written to an intermediate storage location and then copied to the final destination via memory dma. ? boot from twi host (bmode = 0x6) the twi host selects the slave with the unique id 0x5f. the processor replies with an acknowledgement and the host then downloads the boot stream. the twi host agent should comply with the philips i 2 c bus specification table 8. booting modes bmode3C0 description 0000 idle no boot 0001 boot from 8- or 16-bit external flash memory 0010 boot from 16-bit asynchronous fifo 0011 boot from serial spi memory (eeprom or flash) 0100 boot from spi host device 0101 boot from serial twi memory (eeprom/flash) 0110 boot from twi host 0111 boot from uart0 host 1000 boot from uart1 host 1001 reserved 1010 boot from sdram 1011 boot from otp memory 1100 boot from 8- bit nand flash via nfc using portf data pins 1101 boot from 8- bit nand flash via nfc using porth data pins 1110 boot from 16-bit host dma 1111 boot from 8-bit host dma
rev. d | page 19 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 version 2.1. an i 2 c multiplexer can be used to select one processor at a time when booting multiple processors from a single twi. ? boot from uart0 host on port g (bmode = 0x7) using an autobaud handshake sequence, a boot-stream for- matted program is downloaded by the host. the host selects a bit rate within the uart clocking capabilities. when performing the autoba ud, the uart expects a @ (0x40) character (eight bits data, one start bit, one stop bit, no parity bit) on the uart0rx pin to determine the bit rate. the uart then replies with an acknowledgement composed of 4 bytes (0xbf, the value of uart0_dll, the value of uart0_dlh, then 0x00). the host can then download the boot stream. to hold off the host the blackfin processor signals the host with the boot host wait (hwait) signal. therefore, the host must monitor hwait before every transmitted byte. ? boot from uart1 host on port f (bmode = 0x8). same as bmode = 0x7 except that the uart1 port is used. ? boot from sdram (bmode = 0xa) this is a warm boot scenario, where the boot kernel starts booting from address 0x0000 0010. the sdram is expe cted to contain a valid boot stream and the sdram cont roller must be configured by the otp settings. ? boot from otp memory (bmode = 0xb) this provides a stand-alone booting method. the boot stream is loaded from on-chip otp memory. by de fault, the boot stream is expected to start from otp pa ge 0x40 and can occupy all public otp memory up to page 0xdf. this is 2560 bytes. since the start page is programmable, the maximum size of the boot stream can be extended to 3072 bytes. ? boot from 8-bit external na nd flash memory (bmode = 0xc and bmode = 0xd) in this mode, auto detection of the nand flash device is performed. bmode = 0xc, the processor configures portf gpio pins pf7:0 for the nand data pins and porth pins ph15:10 for the nand control signals. bmode = 0xd, the processor configures porth gpio pins ph7:0 for the nand data pins and porth pins ph15:10 for the nand control signals. for correct device operation pu ll-up resistors are required on both nd_ce (ph10) and nd_busy (ph13) signals. by default, a value of 0x0033 is written to the nfc_ctl regis- ter. the booting procedure always starts by booting from byte 0 of block 0 of the nand flash device. nand flash boot supports the following features: device auto detection error detection & correction for maximum reliability no boot stream size limitation peripheral dma providing efficient transfer of all data (excluding the ecc parity data) software-configurable boot mode for booting from boot streams spanning mult iple blocks, including bad blocks software-configurable boot mode for booting from multiple copies of the boot stream, allowing for han- dling of bad blocks and uncorrectable errors configurable timing via otp memory small page nand flash device s must have a 512-byte page size, 32 pages per block, a 16-byte spare area size, and a bus configuration of 8 bits. by defa ult, all read requests from the nand flash are followed by four address cycles. if the nand flash device requires only three address cycles, the device must be capable of ignoring the additional address cycles. the small page nand flash device must comply with the following command set: reset: 0xff read lower half of page: 0x00 read upper half of page: 0x01 read spare area: 0x50 for large-page nand-flash de vices, the four-byte elec- tronic signature is read in order to configure the kernel for booting, which allows support for multiple large-page devices. the fourth byte of the electronic signature must comply with the specification in table 9 on page 20 . any nand flash array configuration from table 9 , exclud- ing 16-bit devices, that also complies with the command set listed below are directly su pported by the boot kernel. there are no restrictions on th e page size or block size as imposed by the small-page boot kernel. for devices consisting of a five -byte signature, only four are read. the fourth must comply as outlined above. large page devices must su pport the following command set: reset: 0xff read electronic signature: 0x90 read: 0x00, 0x30 (confirm command) large-page devices must not support or react to nand flash command 0x50. this is a small-page nand flash command used for device auto detection. by default, the boot kernel will always issue five address cycles; therefore, if a large page device requires only four cycles, the device must be capable of ignoring the addi- tional address cycles. ? boot from 16-bit host dma (bmode = 0xe) in this mode, the host dma port is configured in 16-bit acknowl- edge mode, with little endian data formatting. unlike other modes, the host is responsibl e for interpreting the boot stream. it writes data blocks individually into the host dma port. before configuring the dma settings for each block, the host may either poll the allow_config bit in host_status or wait to be interrupted by the hwait
rev. d | page 20 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 signal. when using hwait, the host must still check allow_config at least once before beginning to con- figure the host dma port. after completing the configuration, the host is requ ired to poll the ready bit in host_status before beginnin g to transfer data. when the host sends an hirq control command, the boot kernel issues a call instruction to ad dress 0xffa0 0000. it is the host's responsibility to ensu re that valid code has been placed at this address. the routine at 0xffa0 0000 can be a simple initialization routine to configure internal resources, such as the sdram controller, which then returns using an rts instructio n. the routine may also by the final application, which will never return to the boot kernel. ? boot from 8-bit host dma (bmode = 0xf) in this mode, the host dma port is configured in 8-bit interrupt mode, with little endian data formatting. unlike other modes, the host is responsibl e for interpreting the boot stream. it writes data blocks individually into the host dma port. before configuring the dma settings for each block, the host may either poll the allow_config bit in host_status or wait to be interrupted by the hwait signal. when using hwait, the host must still check allow_config at least once before beginning to con- figure the host dma port. the host will receive an interrupt from the host_ack signal every time it is allowed to send the next fifo depths worth (sixteen 32-bit words) of information. when the host sends an hirq con- trol command, the boot kernel issues a call instruction to address 0xffa0 0000. it is th e host's responsibility to ensure valid code has been plac ed at this address. the rou- tine at 0xffa0 0000 can be a si mple initializa tion routine to configure internal resour ces, such as the sdram con- troller, which then returns using an rts instruction. the routine may also by the final application, which will never return to the boot kernel. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to a very small final memory size. th e instruction set also provides fully featured multifunction in structions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm /application code) and super- visor (o/s kernel, device drivers, debuggers, isrs) modes of operation, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mc u features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store mo dified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, providing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, which include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded in 16 bits. development tools analog devices supports its proce ssors with a complete line of software and hardware development tools, including integrated development environments (which include crosscore ? embed- ded studio and/or visualdsp++ ? ), evaluation products, emulators, and a wide variety of software add-ins. integrated development environments (ides) for c/c++ software writing and editing, code generation, and debug support, analog devices offers two ides. the newest ide, crosscore embe dded studio, is based on the eclipse tm framework. supporting most analog devices proces- sor families, it is the ide of choice for future processors, including multicore devices. crosscore embedded studio seamlessly integrates available so ftware add-ins to support real time operating systems, file systems, tcp/ip stacks, usb stacks, algorithmic software modules, and evaluation hardware board support packages. for more information, visit www.ana- log.com/cces . table 9. fourth byte for large page devices bit parameter value meaning d1:d0 page size (excluding spare area) 00 01 10 11 1k byte 2k byte 4k byte 8k byte d2 spare area size 00 01 8 byte/512 byte 16 byte/512 byte d5:d4 block size (excluding spare area) 00 01 10 11 64k byte 128k byte 256k byte 512k byte d6 bus width 00 01 x8 not supported d3, d7 not used for configuration
rev. d | page 21 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 the other analog devices ide, visualdsp++, supports proces- sor families introduced prior to the release of crosscore embedded studio. this ide includes the analog devices vdk real time operating system and an open source tcp/ip stack. for more information visit www.analog.com/visualdsp . note that visualdsp++ will not support future analog devices processors. ez-kit lite evaluation board for processor evaluation, analog devices provides wide range of ez-kit lite ? evaluation boards. incl uding the processor and key peripherals, the evaluation board also supports on-chip emulation capabilities and other evaluation and development features. also available are various ez-extenders ? , which are daughter cards delivering additional specialized functionality, including audio and video processing. for more information visit www.analog.com and search on ezkit or ezextender. ez-kit lite evaluation kits for a cost-effective way to learn more about developing with analog devices processors, analog devices offer a range of ez- kit lite evaluation kits. each evaluation kit includes an ez-kit lite evaluation board, directions for downloading an evaluation version of the available ide(s), a usb cable, and a power supply. the usb controller on the ez-kit lite board connects to the usb port of the users pc, enab ling the chosen ide evaluation suite to emulate the on-board processor in-circuit. this permits the customer to download, execut e, and debug programs for the ez-kit lite system. it also su pports in-circuit programming of the on-board flash device to store user-specific boot code, enabling standalone operation. with the full version of cross- core embedded studio or visualdsp++ installed (sold separately), engineers can deve lop software for supported ez- kits or any custom system util izing supported analog devices processors. software add-ins for cr osscore embedded studio analog devices offers software add-ins which seamlessly inte- grate with crosscore embedded stud io to extend its capabilities and reduce development time. add-ins include board support packages for evaluation hardwa re, various middleware pack- ages, and algorithmic modules. documentation, help, configuration dialogs, and coding examples present in these add-ins are viewable through th e crosscore embedded studio ide once the add-in is installed. board support packages for evaluation hardware software support for the ez-kit lite evaluation boards and ez- extender daughter cards is prov ided by software add-ins called board support packages (bsps). the bsps contain the required drivers, pertinent release notes, and select example code for the given evaluation hardware. a downlo ad link for a specific bsp is located on the web page for the associated ez-kit or ez- extender product. the link is found in the product download area of the product web page. middleware packages analog devices separately offers middleware add-ins such as real time operating systems, fi le systems, usb stacks, and tcp/ ip stacks. for more informatio n see the following web pages: ? www.analog.com/ucos3 ? www.analog.com/ucfs ? www.analog.com/ucusbd ? www.analog.com/lwip algorithmic modules to speed development, analog devices offers add-ins that per- form popular audio and video pr ocessing algorithms. these are available for use with both cr osscore embedded studio and visualdsp++. for more information visit www.analog.com and search on blackfin software modules or sharc software modules. designing an emulator-compatible dsp board (target) for embedded system test and debug, analog devices provides a family of emulators. on each jtag dsp, analog devices sup- plies an ieee 1149.1 jtag test access port (tap). in-circuit emulation is facilitated by use of this jtag interface. the emu- lator accesses the processors internal features via the processors tap, allowing the de veloper to load code, set break- points, and view variables, memory, and registers. the processor must be halted to se nd data and commands, but once an operation is completed by the emulator, the dsp system is set to run at full speed with no im pact on system timing. the emu- lators require the target board to include a header that supports connection of the dsps jt ag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connection s, signal buffering, signal ter- mination, and emulator pod logic, see the engineer-to-engineer note analog devices jtag emul ation technical reference (ee-68) on the analog devices website ( www.analog.com )use site search on ee-68. this do cument is updated regularly to keep pace with improvements to emulator support. additional information the following publications that describe the adsp-bf52x pro- cessors (and related processors) can be ordered from any analog devices sales office or accessed electronically on our website: ? getting started with blackfin processors ? adsp-bf52x blackfin proc essor hardware reference (vol- umes 1 and 2) ? blackfin processor programming reference ? adsp-bf522/adsp-bf524/adsp-bf526 blackfin proces- sor anomaly list ? adsp-bf523/adsp-bf525/adsp-bf527 blackfin proces- sor anomaly list
rev. d | page 22 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 related signal chains a signal chain is a series of signal-conditioning electronic com- ponents that receive input (data acquired from sampling either real-time phenomena or from stor ed data) in tandem, with the output of one portion of the ch ain supplying input to the next. signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real-time phenomena. for more information about this term and related topics, see the signal chain entry in wikipedia or the glossary of ee terms on the analog devices website. analog devices eases signal proc essing system development by providing signal proc essing components that are designed to work together well. a tool for viewing relationships between specific applications and related components is available on the www.analog.com website. the application signal chains pa ge in the circuits from the lab tm site ( http:\\www.analog.com\signalchains ) provides: ? graphical circuit block diag ram presentation of signal chains for a variety of circuit types and applications ? drill down links for components in each chain to selection guides and application information ? reference designs applying best practice design techniques lockbox secure technology disclaimer analog devices products containing lockbox secure technol- ogy are warranted by analog devices as detailed in the analog devices standard terms and conditions of sale. to our knowl- edge, the lockbox secure technolo gy, when used in accordance with the data sheet and hardware reference manual specifica- tions, provides a secure method of implementing code and data safeguards. however, analog devices does not guarantee that this technology provides absolute security. accordingly, analog devices hereby disclaims any and all express and implied warranties that the lockbox secure technology cannot be breached, compromised, or otherwise cir- cumvented and in no event shall analog devices be liable for any loss, damage, destruction, or release of data, information, physical property, or intellectual property.
rev. d | page 23 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 signal descriptions signal definitions for the adsp-b f52x processors are listed in table 10 . in order to maintain ma ximum function and reduce package size and ball count, some balls have dual, multiplexed functions. in cases where ball function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. all pins are three-stated during and immediately after reset, with the exception of the external memory interface, asynchro- nous and synchronous memory control, and the buffered xtal output pin (clkbuf). on the external memory interface, the control and address lines are driv en high, with the exception of clkout, which toggles at the sy stem clock rate. during hiber- nate, all outputs are three-stat ed unless otherwise noted in table 10 . all i/o pins have their input buffers disabled with the exception of the pins that need pull-up s or pull-downs, as noted in table 10 . it is strongly advised to use the available ibis models to ensure that a given board design meet s overshoot/undershoot and sig- nal integrity requirements. if no ibis simulation is performed, it is strongly recommended to add se ries resistor terminations for all driver types a, c and d. the termination resistor s should be placed near the processor to reduce transients and improve si gnal integrity. the resistance value, typically 33 or 47 , sh ould be chosen to match the average board trace impedance. additionally, adding a paralle l termination to clkout may prove useful in further enhancing signal integrity. be sure to verify overshoot/undershoot and si gnal integrity specifications on actual hardware. table 10. signal descriptions signal name type function driver type 1 ebiu addr19C1 o address bus a data15C0 i/o data bus a abe1C0 / sdqm1C0 o byte enables/ data mask a ams3C0 o asynchronous memory bank selects (require pull-ups if hibernate is used.) a ardy i hardware ready control aoe o asynchronous output enable a are o asynchronous read enable a awe o asynchronous write enable a sras o sdram row address strobe a scas o sdram column address strobe a swe osdram write enable a scke o sdram clock enable (requires a pu ll-down if hibernate with sdram self- refresh is used.) a clkout o sdram clock output b sa10 o sdram a10 signal a sms o sdram bank select a
rev. d | page 24 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 usb 2.0 hs otg usb_dp i/o data + (this ball should be pulled low when usb is unused or not present.) f usb_dm i/o data C (this ball should be pulled low when usb is unused or not present.) f usb_xi i usb crystal input (this ball should be pulled low when usb is unused or not present.) usb_xo o usb crystal output (this ball should be left unconnected when usb is unused or not present.) f usb_id i usb otg mode (this ball should be pulled low when usb is unused or not present.) usb_vref a usb voltage reference (connect to gnd through a 0.1 f capacitor or leave unconnected when not used.) usb_rset a usb resistance set. (this ball should be left unconnected.) usb_vbus i/o 5v usb vbus. usb_vbus is an output only in peripheral mode during srp signaling. host mode requires that an external voltage source of 5 v at 8 ma or more (per the otg specification) be applied to vbus. the voltage source needs to be able to charge and discharge vbus, thus an on/off switch is required to control the voltage source. a gpio can be used for this purpose (this ball should be pulled low when usb is unused or not present.) f port f: gpio and multiplexed peripherals pf0/ ppi d0 / dr0pri / nd_d0a i/o gpio/ ppi data 0 / sport0 primary receive data / nand alternate data 0 c pf1/ ppi d1 / rfs0 / nd_d1a i/o gpio/ ppi data 1 / sport0 receive frame sync / nand alternate data 1 c pf2/ ppi d2 / rsclk0 / nd_d2a i/o gpio/ ppi data 2 / sport0 receive serial clock / nand alternate data 2 / alternate capture input 0 d pf3/ ppi d3 / dt0pri / nd_d3a i/o gpio/ ppi data 3 / sport0 transmit primary data / nand alternate data 3 c pf4/ ppi d4 / tfs0 / nd_d4a / taclk0 i/o gpio/ ppi data 4 / sport0 transmit frame sync / nand alternate data 4/alternate timer clock 0 c pf5/ ppi d5 / tsclk0 / nd_d5a / taclk1 i/o gpio/ ppi data 5 / sport0 transmit serial clock / nand alternate data 5 / alternate timer clock 1 d pf6/ ppi d6/dt0sec / nd_d6a / taci0 i/o gpio/p pi data 6 / sport0 transmit secondary data / nand alternate data 6 / alternate capture input 0 c pf7/ ppi d7 / dr0sec / nd_d7a/taci1 i/o gpio/ ppi data 7 / sport0 receive secondary data / nand alternate data 7 / alternate capture input 1 c pf8/ ppi d8 / dr1pri i/o gpio/ ppi data 8 / sport1 primary receive data c pf9/ ppi d9 / rsclk1 / spisel6 i/o gpio/ ppi data 9 / sport1 receive serial clock / spi slave select 6 d pf10/ ppi d10 / rfs1 / spisel7 i/o gpio/ ppi data 10 / sport1 receive frame sync / spi slave select 7 c pf11/ ppi d11 / tfs1 / czm i/o gpio/ ppi data 11 / sport1 transmit frame sync / counter zero marker c pf12/ ppi d12 / dt1pri / spisel2 / cdg i/o gpio/ ppi data 12 / sport1 transmit primary data / spi slave select 2 / counter down gate c pf13/ ppi d13 / tsclk1 / spisel3 / cud i/o gpio/ ppi data 13 / sport1 transmit serial clock / spi slave select 3 / counter up direction d pf14/ ppi d14 / dt1sec / uart1tx i/o gpio/ ppi data 14 / sport1 transmit secondary data / uart1 transmit c pf15/ ppi d15 / dr1sec / uart1rx / taci3 i/o gpio/ ppi data 15 / sport1 receive secondary data / uart1 receive /alternate capture input 3 c table 10. signal descriptions (continued) signal name type function driver type 1
rev. d | page 25 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 port g: gpio and multiplexed peripherals pg0/ hwait i/o gpio/ boot host wait 2 c pg1/ spiss / spisel1 i/o gpio/ spi slave select input / spi slave select 1 c pg2/ sck i/o gpio/ spi clock d pg3/ miso / dr0seca i/o gpio/ spi master in slave out / sport 0 alternate receive data secondary c pg4/ mosi / dt0seca i/o gpio/ spi master out slave in / sport 0 alternate transmit data secondary c pg5/ tmr1 / ppi_fs2 i/o gpio/ timer1 / ppi frame sync2 c pg6/ dt0pria / tmr2 / ppi_fs3 i/o gpio/ sport0 alternate primary transmit data / timer2 / ppi frame sync3 c pg7/ tmr3 / dr0pria / uart0tx i/o gpio/ timer3 / sport 0 alternate receive data primary / uart0 transmit c pg8/ tmr4 / rfs0a / uart0rx / taci4 i/o gpio/ timer 4 / sport 0 alternate receive clock/frame sync / uart0 receive / alternate capture input 4 c pg9/ tmr5 / rsclk0a / taci5 i/o gpio/ timer5 / sport 0 alternate receive clock / alternate capture input 5 d pg10/ tmr6 / tsclk0a / taci6 i/o gpio/ timer 6 / sport 0 alternate transmit / alternate capture input 6 d pg11/ tmr7 / host_wr i/o gpio/ timer7 / host dma write enable c pg12/ dmar1 / uart1txa / host_ack i/o gpio/ dma request 1 / alternate uart1 transmit / host dma acknowledge c pg13/ dmar0 / uart1rxa / host_addr / taci2 i/o gpio/ dma request 0 / alternate uart1 receive / host dma address / alternate capture input 2 c pg14/ tsclk0a1 / mdc / host_rd i/o gpio/ sport0 alternate 1 transmit / ethernet management channel clock / host dma read enable d pg15 3 / tfs0a / mii phyint / rmii mdint / host_ce i/o gpio/ sport0 alternate transmit frame sync / ethernet / mii phy interrupt / rmii management channel data interrupt / host dma chip enable c port h: gpio and multiple xed peripherals ph0/ nd_d0 / miicrs / rmiicrsdv / host_d0 i/o gpio/ nand d0 / ethernet mii or rmii carrier sense / host dma d0 c ph1/ nd_d1 / erxer / host_d1 i/o gpio/ nand d1 / ethernet mii or rmii receive error / host dma d1 c ph2/ nd_d2 / mdio / host_d2 i/o gpio/ nand d2 / ethernet management channel serial data / host dma d2 c ph3/ nd_d3 / etxen / host_d3 i/o gpio/ nand d3 / ethernet mii transmit enable / host dma d3 c ph4/ nd_d4 / miitxclk / rmiiref_clk / host_d4 i/o gpio/ nand d4 / ethernet mii or rmii reference clock / host d4 c ph5/ nd_d5 / etxd0 / host_d5 i/o gpio/ nand d5 / ethernet mii or rmii transmit d0 / host dma d5 c ph6/ nd_d6 / erxd0 / host_d6 i/o gpio/ nand d6 / ethernet mii or rmii receive d0 / host dma d6 c ph7/ nd_d7 / etxd1 / host_d7 i/o gpio/ nand d7 / ethernet mii or rmii transmit d1 / host dma d7 c ph8/ spisel4 / erxd1 / host_d8 / taclk2 i/o gpio/ alternate timer clock 2 / ethernet mii or rmii receive d1 / host dma d8 / spi slave select 4 c ph9/ spisel5 / etxd2 / host_d9 / taclk3 i/o gpio/ spi slave select 5 / ethernet mii transmit d2 / host dma d9 / alternate timer clock 3 c ph10/ nd_ce / erxd2 / host_d10 i/o gpio/ nand chip enable / ethernet mii receive d2 / host dma d10 c ph11/ nd_we / etxd3 / host_d11 i/o gpio/ nand write enable / ethernet mii transmit d3 / host dma d11 c ph12/ nd_re / erxd3 / host_d12 i/o gpio/ nand read enable / ethernet mii receive d3 / host dma d12 c ph13/ nd_busy / erxclk / host_d13 i/o gpio/ nand busy / ethernet mii receive clock / host dma d13 c ph14/ nd_cle / erxdv / host_d14 i/o gpio/ nand command latch enable / ethernet mii or rmii receive data valid / host dma d14 c ph15/ nd_ale / col / host_d15 i/o gpio/ nand address latch enable / ethernet mii collision / host dma data 15 c table 10. signal descriptions (continued) signal name type function driver type 1
rev. d | page 26 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 port j: multiplexed peripherals pj0: ppi_fs1/ tmr0 i/o ppi frame sync1/ timer0 c pj1: ppi_clk/ tmrclk i ppi clock/ timer clock pj2: scl i/o 5v twi serial clock (this pin is an open-drain output and requires a pull-up resistor. 4 ) e pj3: sda i/o 5v twi serial data (this pin is an open-drain output and requires a pull-up resistor. 4 ) e real time clock rtxi i rtc crystal input (this ball should be pulled low when not used.) rtxo o rtc crystal output (does not three-state during hibernate.) jtag port tck i jtag clock tdo o jtag serial data out c tdi i jtag serial data in tms i jtag mode select trst i jtag reset (this ball should be pulled low if the jtag port is not used.) emu o emulation output c clock clkin i clock/crystal input xtal o crystal output (if clkbuf is enabled, does not three-state during hibernate.) clkbuf o buffered xtal output (if enabled, does not three-state during hibernate.) c mode controls reset i reset nmi i nonmaskable interrupt (this ball should be pulled high when not used.) bmode3C0 i boot mode strap 3-0 adsp-bf523/adsp-bf525/adsp-bf527 voltage regulation i/f vr sel i internal/external voltage regulator select vr out /ext_wake1 o external fet drive/wake up in dication 1 (does not three-state during hibernate.) g ext_wake0 o wake up indication 0 (does not three-state during hibernate.) c ss/pg a soft start/power good adsp-bf522/adsp-bf524/adsp-bf526 voltage regulation i/f ext_wake1 o wake up indication 1 (does not three-state during hibernate.) c ext_wake0 o wake up indication 0 (does not three-state during hibernate.) c pg a power good (this signal should be pulled low when not used.) table 10. signal descriptions (continued) signal name type function driver type 1
rev. d | page 27 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 power supplies all supplies must be powered see operating conditions for adsp-bf523/adsp-bf525/adsp-bf527 processors on page 30 , and see operating conditions for adsp-bf522/ adsp-bf524/adsp-bf526 processors on page 28 . v ddext pi/o power supply v ddint p internal power supply v ddrtc p real time clock power supply v ddusb p 3.3 v usb phy power supply v ddmem pmem power supply v ddotp potp power supply v ppotp p otp programming voltage gnd g ground for all supplies 1 see output drive currents on page 73 for more information about each driver type. 2 hwait must be pulled high or lo w to configure polarity. it is driven as an output and toggle during processor boot. see booting modes on page 18 . 3 when driven low, this ball can be used to wake up the processor from the hibernate st ate, either in normal gpio mode or in ethe rnet mode as mii phyint . if the ball is used for wake up, enable the feature wi th the phywe bit in the vr_ctl register, and pull-up the ball with a resistor. 4 consult version 2.1 of the i 2 c specification for the proper resistor value. table 10. signal descriptions (continued) signal name type function driver type 1
rev. d | page 28 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 specifications specifications are subject to change without notice. operating conditions for adsp-bf522/adsp-bf524/adsp-bf526 processors parameter conditions min nominal max unit v ddint internal supply voltage 1.235 1.47 v v ddext external supply voltage 1 1 must remain powered (even if the as sociated function is not used). 1.7 1.8 1.9 v v ddext external supply voltage 1 2.25 2.5 2.75 v v ddext external supply voltage 1 33.33.6v v ddrtc rtc power supply voltage 2 2 if not used, power with v ddext . 2.25 3.6 v v ddmem mem supply voltage 1, 3 3 balls that use v ddmem are data15C0, addr19C1, abe1C0 , are , awe , aoe , ams3C0 , ardy, sa10, swe , scas , clkout, sras , sms , scke. these balls are not tolerant to voltages higher than v ddmem . 1.7 1.8 1.9 v v ddmem mem supply voltage 1, 3 2.25 2.5 2.75 v v ddmem mem supply voltage 1, 3 33.33.6v v ddotp otp supply voltage 1 2.25 2.5 2.75 v v ppotp otp programming voltage 1 for reads 2.25 2.5 2.75 v for writes 4 4 the v ppotp voltage for writes must only be applied when programming otp memo ry. there is a finite amount of cumulative time that this vol tage may be applied (dependent on voltage and junction temperature) over the lifetime of the part. please see table 30 on page 38 for details. 6.9 7.0 7.1 v v ddusb usb supply voltage 5 5 when not using the usb peripheral on th e adsp-bf524/adsp-bf52 6 or terminating v ddusb on the adsp-bf522, v ddusb must be powered by v ddext . 3.0 3.3 3.6 v v ih high level input voltage 6, 7 6 parameter value applies to all input and bidirectional balls, except usb_d p, usb_dm, usb_vbus, sda, and scl. 7 bidirectional balls (pf15C0, pg15C0, ph15C0) and input balls (rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode3C0) of the ad sp-bf52x processors are 2.5 v tolerant (always accept up to 2.7 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. v ddext /v ddmem = 1.90 v 1.1 v v ih high level input voltage 6, 8 8 bidirectional balls (pf15C0, pg15C0, ph15C0) and input balls (rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode3C0) of the ad sp-bf52x processors are 3.3 v tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. v ddext /v ddmem = 2.75 v 1.7 v v ih high level input voltage 6, 8 v ddext /v ddmem = 3.6 v 2.0 v v ihtwi 9 9 the v ihtwi min and max value vary with the selection in the twi_dt field of the nongpio_drive register. see v bustwi min and max values in table 11 . high level input voltage v ddext = 1.90 v/2.75 v/3.6 v 0.7 v bustwi v bustwi v v il low level input voltage 6, 7 v ddext /v ddmem = 1.7 v 0.6 v v il low level input voltage 6, 8 v ddext /v ddmem = 2.25 v 0.7 v v il low level input voltage 6, 8 v ddext /v ddmem = 3.0 v 0.8 v v iltwi low level input voltage v ddext = minimum 0.3 v bustwi 10 10 sda and scl are pulled up to v bustwi . see table 11 . v t j junction temperature 289-ball csp_bga @t ambient =0c to +70c 0+105c t j junction temperature 208-ball csp_bga @t ambient =0c to +70c 0+105c t j junction temperature 208-ball csp_bga @t ambient = C40c to +85c C40 +105 c
rev. d | page 29 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 11 shows settings for twi_dt in the nongpio_drive register. set this register prior to using the twi port. clock related operating conditions for adsp-bf522/adsp-bf524/adsp-bf526 processors table 12 describes the core clock ti ming requirements for the adsp-bf522/adsp-bf524/adsp-bf 526 processors. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock and system clock (see table 14 ). table 13 describes phase-locked loop operating conditions. table 11. twi_dt field selections and v ddext /v bustwi twi_dt v ddext nominal v bustwi min v bustwi nominal v bustwi max unit 000 (default) 1 3.3 2.97 3.3 3.63 v 001 1.8 1.7 1.8 1.98 v 010 2.5 2.97 3.3 3.63 v 011 1.8 2.97 3.3 3.63 v 100 3.3 4.5 5 5.5 v 101 1.8 2.25 2.5 2.75 v 110 2.5 2.25 2.5 2.75 v 111 (reserved)CCCCC 1 designs must comply with the v ddext and v bustwi voltages specified for the default twi_dt setting for correct jtag boundary scan operation during reset. table 12. core clock (cclk) requirements (all instruction rates 1 ) for adsp-bf522/adsp-bf524/adsp-bf526 processors parameter nominal voltage setting max unit f cclk core clock frequency (v ddint =1.33 v minimum) 1.40 v 400 2 mhz f cclk core clock frequency (v ddint = 1.235 v minimum) 1.30 v 300 mhz 1 see the ordering guide on page 88 . 2 applies to 400 mhz models only. see the ordering guide on page 88 . table 13. phase-locked loop operating conditions for adsp-bf522/adsp-bf 524/adsp-bf526 processors parameter min max unit f vco voltage controlled oscillator (vco) frequency 70 instruction rate 1 mhz 1 see the ordering guide on page 88 . table 14. sclk conditions for adsp-b f522/adsp-bf524/adsp-bf526 processors parameter v ddext /v ddmem 1.8 v nominal 1 v ddext /v ddmem 2.5 v or 3.3 v nominal max max unit f sclk clkout/sclk frequency (v ddint 1.33 v) 2 80 100 mhz f sclk clkout/sclk frequency (v ddint < 1.33 v) 80 80 mhz 1 if either v ddext or v ddmem are operating at 1.8 v nominal, f sclk is constrained to 80 mhz. 2 f sclk must be less than or equal to f cclk and is subject to additional restrict ions for sdram interface operation. see table 37 on page 47 .
rev. d | page 30 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 operating conditions for adsp-bf 523/adsp-bf525/adsp-bf527 processors parameter conditions min nominal max unit v ddint internal supply voltage 1 1 the voltage regulator can generate v ddint at levels of 1.00 v to 1.20 v with C5% to +5% tolerance when vrctl is programmed with the bfrom_syscontrol() api. this specification is only guaranteed when the api is used. nonautomotive models 2 2 see ordering guide on page 88 . 0.95 1.26 v v ddint internal supply voltage 1 automotive 533 mhz models 3 3 see automotive products on page 87 . 1.093 1.15 1.26 v v ddint internal supply voltage 1 automotive 400 mhz models 3 1.045 1.10 1.20 v v ddext external supply voltage 4, 5 4 must remain powered (even if the as sociated function is not used). 5 v ddext is the supply to the voltage regulator and gpio. nonautomotive models, internal voltage regulator disabled 1.7 1.8 1.9 v v ddext external supply voltage 4, 5 nonautomotive models 2.25 2.5 2.75 v v ddext external supply voltage 4, 5 nonautomotive models 3 3.3 3.6 v v ddext external supply voltage 4, 5 automotive models 2.7 3.3 3.6 v v ddrtc rtc power supply voltage 6 6 if not used, power with v ddext . nonautomotive models 2.25 3.6 v v ddrtc rtc power supply voltage 6 automotive models 2.7 3.3 3.6 v v ddmem mem supply voltage 4, 7 7 balls that use v ddmem are data15C0, addr19C1, abe1C0 , are , awe , aoe , ams3C0 , ardy, sa10, swe , scas , clkout, sras , sms , scke. these balls are not tolerant to voltages higher than v ddmem . nonautomotive models 1.7 1.8 1.9 v v ddmem mem supply voltage 4, 7 nonautomotive models 2.25 2.5 2.75 v v ddmem mem supply voltage 4, 7 nonautomotive models 3 3.3 3.6 v v ddmem mem supply voltage 4, 7 automotive models 2.7 3.3 3.6 v v ddotp otp supply voltage 4 2.25 2.5 2.75 v v ppotp otp programming voltage 4 2.25 2.5 2.75 v v ddusb usb supply voltage 8 8 when not using the usb peripheral on th e adsp-bf525/adsp-bf52 7 or terminating v ddusb on the adsp-bf523, v ddusb must be powered by v ddext . 3.0 3.3 3.6 v v ih high level input voltage 9, 10 9 bidirectional balls (pf15C0, pg15C0, ph15C0) and input balls (rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode3C0) of the ad sp-bf52x processors are 2.5 v tolerant (always accept up to 2.7 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. 10 parameter value applies to all input and bidirectional balls, except usb_dp, usb_dm, usb_vbus, sda, and scl. v ddext /v ddmem = 1.90 v 1.1 v v ih high level input voltage 10, 11 11 bidirectional balls (pf15C0, pg1 5C0, ph15C0) and input balls (rtxi, tck, tdi, tms, trst , clkin, reset , nmi , and bmode3C0) of the adsp-bf52x processors are 3.3 v tolerant (always accept up to 3.6 v maximum v ih ). voltage compliance (on outputs, v oh ) is limited by the v ddext supply voltage. v ddext /v ddmem = 2.75 v 1.7 v v ih high level input voltage 10, 11 v ddext /v ddmem = 3.6 v 2.0 v v ihtwi high level input voltage 12 12 the v ihtwi min and max value vary with the selection in the twi_dt field of the nongpio_drive register. see v bustwi min and max values in table 11 on page 29 . v ddext = 1.90 v/2.75 v/3.6 v 0.7 v bustwi v bustwi v v il low level input voltage 9, 10 v ddext /v ddmem = 1.7 v 0.6 v v il low level input voltage 10, 11 v ddext /v ddmem = 2.25 v 0.7 v v il low level input voltage 10, 11 v ddext /v ddmem = 3.0 v 0.8 v v iltwi low level input voltage v ddext = minimum 0.3 v bustwi 13 13 sda and scl are pulled up to v bustwi . see table 11 on page 29 . v t j junction temperature 289-ball csp_bga @t ambient =0c to +70c 0 +105 c t j junction temperature 289-ball csp_bga @t ambient = C40c to +70c C40 +105 c t j junction temperature 208-ball csp_bga @t ambient =0c to +70c 0 +105 c t j junction temperature 208-ball csp_bga @t ambient = C40c to +85c C40 +105 c
rev. d | page 31 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 clock related operating conditions for adsp-bf523/adsp-bf525/adsp-bf527 processors table 15 describes the core clock ti ming requirements for the adsp-bf523/adsp-bf525/adsp-bf 527 processors. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock and system clock (see table 17 ). table 16 describes phase-locked loop operating conditions. use the nominal voltage setting ( table 15 ) for internal and external regulators. table 15. core clock (cclk) requirements (all instruction rates 1 ) for adsp-bf523/adsp-bf525/adsp-bf527 processors parameter nominal voltage setting max unit f cclk core clock frequency (v ddint =1.14 v minimum) 1.20 v 600 2 mhz f cclk core clock frequency (v ddint =1.093 v minimum) 1.15 v 533 3 mhz f cclk core clock frequency (v ddint = 1.045 v minimum) 4 1.10 v 400 mhz f cclk core clock frequency (v ddint = 0.95 v minimum) 1.0 v 400 mhz 1 see the ordering guide on page 88 . 2 applies to 600 mhz models only. see the ordering guide on page 88 . 3 applies to 533 mhz and 600 mhz models only. see the ordering guide on page 88 . 4 applies only to auto motive products. see automotive products on page 87 . table 16. phase-locked loop operating conditions for adsp-bf523/adsp-bf525/adsp-bf527 processors parameter min max unit f vco voltage controlled oscillator (vco) frequency (commercial/industrial models) 60 instruction rate 1 mhz f vco voltage controlled oscillator (vco) frequency (automotive models) 70 instruction rate 1 mhz 1 see the ordering guide on page 88 . table 17. sclk conditions for adsp-b f523/adsp-bf525/adsp-bf527 processors v ddext /v ddmem 1.8 v nominal 1 v ddext /v ddmem 2.5 v or 3.3 v nominal parameter max max unit f sclk clkout/sclk frequency (v ddint 1.14 v) 2 100 133 3 mhz f sclk clkout/sclk frequency (v ddint < 1.14 v) 2 100 100 mhz 1 if either v ddext or v ddmem are operating at 1.8 v nominal, f sclk is constrained to 100 mhz. 2 f sclk must be less than or equal to f cclk and is subject to additional restrict ions for sdram interface operation. see table 38 on page 47 . 3 rounded number. actual test specificat ion is sclk period of 7.5 ns. see table 38 on page 47 .
rev. d | page 32 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 electrical characteristics table 18. common electrical characteri stics for all adsp-bf52x processors parameter test conditions min typical max unit v oh high level output voltage v ddext /v ddmem = 1.7 v, i oh =C0.5ma 1.35 v v oh high level output voltage v ddext /v ddmem = 2.25 v, i oh =C0.5ma 2.0 v v oh high level output voltage v ddext /v ddmem = 3.0 v, i oh =C0.5ma 2.4 v v ol low level output voltage v ddext /v ddmem = 1.7 v/2.25 v/ 3.0 v, i ol =2.0ma 0.4 v i ih high level input current 1 1 applies to input balls. v ddext /v ddmem =3.6 v, v in =3.6v 10.0 a i il low level input current 1 v ddext /v ddmem =3.6 v, v in = 0 v 10.0 a i ihp high level input current jtag 2 2 applies to jtag input balls (tck, tdi, tms, trst) . v ddext = 3.6 v, v in = 3.6 v 75.0 a i ozh three-state leakage current 3 3 applies to three-statable balls. v ddext /v ddmem = 3.6 v, v in =3.6v 10.0 a i ozhtwi three-state leakage current 4 4 applies to bidirection al balls scl and sda. v ddext =3.0 v, v in = 5.5 v 10.0 a i ozl three-state leakage current 3 v ddext /v ddmem = 3.6 v, v in = 0 v 10.0 a c in input capacitance 5,6 5 applies to all signal ba lls, except scl and sda. 6 guaranteed, but not tested. f in = 1 mhz, t ambient = 25c, v in =2.5v 58pf c intwi input capacitance 4,6 f in = 1 mhz, t ambient = 25c, v in =2.5v 15 pf
rev. d | page 33 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 19. electrical characteristics for ad sp-bf522/adsp-bf524/adsp-bf526 processors parameter test conditions min typical max unit i dddeepsleep 1 v ddint current in deep sleep mode v ddint = 1.3 v, f cclk = 0 mhz, f sclk =0mhz, t j = 25c, asf = 0.00 2ma i ddsleep v ddint current in sleep mode v ddint = 1.3 v, f sclk = 25 mhz, t j = 25c 13 ma i dd-idle v ddint current in idle v ddint = 1.3 v, f cclk = 300 mhz, f sclk = 25 mhz, t j = 25c, asf = 0.4 44 ma i dd-typ v ddint current v ddint = 1.3 v, f cclk = 300 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 83 ma i dd-typ v ddint current v ddint = 1.4 v, f cclk = 400 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 114 ma i ddhibernate 1, 2 hibernate state current v ddext =v ddmem =v ddrtc =v ddusb =3.30v, v ddotp =v ppotp =2.5 v, t j = 25c, clkin = 0 mhz with voltage regulator off (v ddint = 0 v) 40 a i ddrtc v ddrtc current v ddrtc = 3.3 v, t j = 25c 20 a i ddusb-fs v ddusb current in full/low speed mode v ddusb = 3.3 v, t j = 25c, full speed usb transmit 9 ma i ddusb-hs v ddusb current in high speed mode v ddusb = 3.3 v, t j = 25c, high speed usb transmit 25 ma i ddsleep 1, 3 v ddinit current in sleep mode f cclk = 0 mhz, f sclk > 0 mhz table 22 + (0.52 v ddint f sclk ) 4 ma 4 i dddeepsleep 1, 3 v ddint current in deep sleep mode f cclk = 0 mhz, f sclk = 0 mhz table 22 ma i ddint 3, 5 v ddint current f cclk > 0 mhz, f sclk 0 mhz table 22 + ( table 23 asf) + (0.52 v ddint f sclk ) ma i ddotp v ddotp current v ddotp = 2.5 v, t j = 25c, otp memory read 2 ma i ddotp v ddotp current v ddotp = 2.5 v, t j = 25c, otp memory write 2 ma i ppotp v ppotp current v ppotp = 2.5 v, t j = 25c, otp memory read 100 a i ppotp v ppotp current v ppotp = see table 30 , t j =25c, otpmemory write 3ma 1 see the adsp-bf52x blackfin processor hardware reference manual for definition of sleep, deep sleep, and hibernate operating modes. 2 includes current on v ddext , v ddusb , v ddmem , v ddotp , and v ppotp supplies. clock inputs are tied high or low. 3 guaranteed maximum specifications. 4 unit for v ddint is v (volts). unit for f sclk is mhz. example: 1.4 v, 75 mhz would be 0.52 1.4 75 = 54.6 ma adder. 5 see table 21 for the list of i ddint power vectors covered.
rev. d | page 34 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 20. electrical characteristics for ad sp-bf523/adsp-bf525/adsp -bf527 processors parameter test conditions min typical max unit i dddeepsleep 1 v ddint current in deep sleep mode v ddint = 1.0 v, f cclk = 0 mhz, f sclk =0mhz, t j = 25c, asf = 0.00 10 ma i ddsleep v ddint current in sleep mode v ddint = 1.0 v, f sclk = 25 mhz, t j = 25c 20 ma i dd-idle v ddint current in idle v ddint = 1.0 v, f cclk = 400 mhz, f sclk = 25 mhz, t j = 25c, asf = 0.44 53 ma i dd-typ v ddint current v ddint = 1.0 v, f cclk = 400 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 94 ma i dd-typ v ddint current v ddint = 1.15 v, f cclk = 533 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 144 ma i dd-typ v ddint current v ddint = 1.2 v, f cclk = 600 mhz, f sclk = 25 mhz, t j = 25c, asf = 1.00 170 ma i ddhibernate 1, 2 hibernate state current v ddext =v ddmem =v ddrtc = v ddusb =3.30v, v ddotp =v ppotp =2.5 v, t j = 25c, clkin = 0 mhz with voltage regulator off (v ddint = 0 v) 40 a i ddrtc v ddrtc current v ddrtc = 3.3 v, t j = 25c 20 a i ddusb-fs v ddusb current in full/low speed mode v ddusb = 3.3 v, t j = 25c, full speed usb transmit 9 ma i ddusb-hs v ddusb current in high speed mode v ddusb = 3.3 v, t j = 25c, high speed usb transmit 25 ma i ddsleep 1, 3 v ddint current in sleep mode f cclk = 0 mhz, f sclk > 0 mhz table 24 + (0.61 v ddint f sclk ) 4 ma 4 i dddeepsleep 1, 3 v ddint current in deep sleep mode f cclk = 0 mhz, f sclk = 0 mhz table 24 ma i ddint 3, 5 v ddint current f cclk > 0 mhz, f sclk 0 mhz table 24 + ( table 25 asf) + (0.61 v ddint f sclk ) ma i ddotp v ddotp current v ddotp = 2.5 v, t j = 25c, otp memory read 1 ma i ddotp v ddotp current v ddotp = 2.5 v, t j = 25c, otp memory write 25 ma i ppotp v ppotp current v ppotp = 2.5 v, t j = 25c, otp memory read 0 ma i ppotp v ppotp current v ppotp = 2.5 v, t j = 25c, otp memory write 0 ma 1 see the adsp-bf52x blackfin processor hardware reference manual for definition of sleep, deep sleep, and hibernate operating modes. 2 includes current on v ddext , v ddusb , v ddmem , v ddotp , and v ppotp supplies. clock inputs are tied high or low. 3 guaranteed maximum specifications. 4 unit for v ddint is v (volts). unit for f sclk is mhz. example: 1.2 v, 75 mhz would be 0.61 1.2 75 = 54.9 ma adder. 5 see table 21 for the list of i ddint power vectors covered.
rev. d | page 35 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 total power dissipation total power dissipation has two components: 1. static, including leakage current 2. dynamic, due to transistor switching characteristics many operating conditions can also affect po wer dissipation, including temperature, voltage, operating frequency, and pro- cessor activity. electrical characteristics on page 32 shows the current dissipation for internal circuitry (v ddint ). i dddeepsleep specifies static power dissipati on as a function of voltage (v ddint ) and temperature (see table 22 or table 24 ), and i ddint specifies the total power specific ation for the listed test condi- tions, including the dynamic comp onent as a function of voltage (v ddint ) and frequency ( table 23 or table 25 ). there are two parts to the dynami c component. the first part is due to transistor switching in the core clock (cclk) domain. this part is subject to an acti vity scaling factor (asf) which represents application code runn ing on the processor core and l1 memories ( table 21 ). the asf is combined with the cclk frequency and v ddint dependent data in table 23 or table 25 to calculate this part. the second part is due to tran sistor switching in the system clock (sclk) domain, which is included in the i ddint specifica- tion equation. table 21. activity scaling factors (asf) 1 1 see estimating power for a sdp-bf534/bf536/bf537 blackfin processors (ee-297) . the power vector information al so applies to the adsp-bf52x processors. i ddint power vector activity scaling factor (asf) i dd-peak 1.29 i dd-high 1.26 i dd-typ 1.00 i dd-app 0.88 i dd-nop 0.72 i dd-idle 0.44 table 22. static current i dd-deepsleep (ma) for adsp-bf522/adsp-b f524/adsp-bf526 processors t j (c) 1 voltage (v ddint ) 1 1.2 v 1.25 v 1.3 v 1.35 v 1.4 v 1.45 v 1.5 v C401.471.421.501.641.852.122.09 C201.671.811.891.952.012.072.12 0 1.972.072.152.222.302.392.47 25 2.49 2.66 2.79 2.92 3.07 3.20 3.36 40 3.12 3.37 3.57 3.75 3.96 4.18 4.40 55 4.07 4.47 4.82 5.11 5.41 5.73 6.06 70 5.77 6.28 6.71 7.17 7.61 8.09 8.60 85 8.32 8.88 9.56 10.25 10.94 11.63 12.36 100 12.11 12.93 13.94 14.76 15.76 16.77 17.83 105 13.78 14.72 15.74 16.81 17.91 19.06 20.27 1 valid temperature and voltage ranges are model-specific. see operating conditions for adsp-bf522/ad sp-bf524/adsp-bf526 pro cessors on page 28 . table 23. dynamic current in cclk domain (ma, with asf = 1.0) 1 for adsp-bf522/adsp-bf 524/adsp-bf526 processors f cclk (mhz) 2 voltage (v ddint ) 2 1.2 v 1.25 v 1.3 v 1.35 v 1.4 v 1.45 v 1.5 v 400 n/a n/a 91.41 95.7 100.11 104.51 109.01 350 n/a n/a 80.56 84.37 88.26 92.17 96.17 300 63.31 66.51 69.78 73.09 76.51 79.93 83.42 250 53.36 56.10 58.88 61.72 64.64 67.56 70.55 200 43.49 45.76 48.08 50.44 52.86 55.28 57.77 100 23.6 24.93 26.29 27.68 29.12 30.56 32.04 1 the values are not guaranteed as standalone maximum specifications. they must be combin ed with static current per the equations of electrical characteristics on page 32 . 2 valid frequency and voltage ra nges are model-specific. see operating conditions for adsp-bf522/adsp-bf524/adsp-bf 526 processors on page 28 .
rev. d | page 36 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 24. static current i dd-deepsleep (ma) for adsp-bf523/adsp-b f525/adsp-bf527 processors t j (c) 1 voltage (v ddint ) 1 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v C40 6.5 7.8 9.3 11.1 13.1 15.4 18.0 21.0 C20 9.0 10.6 12.4 14.6 17.0 19.8 22.9 26.4 0 13.2 15.2 17.7 20.4 23.5 27.0 30.9 35.3 25 22.3 25.4 28.9 32.8 37.2 42.1 47.6 53.7 40 30.8 34.8 39.2 44.1 49.6 55.7 62.5 70.0 55 42.9 47.9 53.6 59.9 66.9 74.6 83.2 92.6 70 59.1 65.6 72.9 80.8 89.7 99.4 110.2 122.0 85 80.4 88.6 97.9 107.8 119.2 131.5 145.1 159.8 100 109.3 118.7 130.5 143.2 157.4 172.8 189.7 208.1 105 120.8 132.1 144.7 158.8 174.2 190.9 209.3 229.2 115 144.4 157.5 172.3 188.4 206.0 225.3 246.4 269.2 125 173.9 189.1 206.4 224.9 245.4 267.8 292.2 318.7 1 valid temperature and voltage ranges are model-specific. see operating conditions for adsp-bf523/adsp-bf 525/adsp-bf527 proce ssors on page 30 . table 25. dynamic current in cclk domain (ma, with asf = 1.0) 1 for adsp-bf523/adsp-bf 525/adsp-bf527 processors f cclk (mhz) 2 voltage (v ddint ) 2 0.95 v 1.00 v 1.05 v 1.10 v 1.15 v 1.20 v 1.25 v 1.30 v 600 n/a n/a n/a n/a 130.4 137.6 145.1 152.5 533 n/a n/a n/a 110.3 116.7 123.3 129.8 136.4 500 n/a n/a 97.3 103.1 109.1 115.0 121.3 127.7 400 69.8 74.3 78.9 83.6 88.5 93.5 98.6 103.9 300 53.4 56.9 60.4 64.1 68.0 71.8 75.8 80.0 200 36.9 39.4 41.9 44.6 47.4 50.1 53.0 56.0 100 20.5 22.0 23.6 25.3 27.0 28.8 30.6 32.5 1 the values are not guaranteed as standalone maximum specifications. they must be combin ed with static current per the equations of electrical characteristics on page 32 . 2 valid frequency and voltage ra nges are model-specific. see operating conditions for adsp-bf523/adsp-bf525/adsp-bf 527 processors on page 30 .
rev. d | page 37 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 absolute maximum ratings stresses greater than those listed in table 26 may cause perma- nent damage to the device. these are stress ratings only. functional operation of the devi ce at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 26 specifies the maximum total source/sink (i oh /i ol ) cur- rent for a group of pins. permanent damage can occur if this value is exceeded. to understand th is specification, if pins ph4, ph3, ph2, ph1, and ph0 from group 1 in table 28 were sourc- ing or sinking 2 ma each, the tota l current for those pins would be 10 ma. this would allow up to 72 ma total that could be sourced or sunk by the remain ing pins in the group without damaging the device. for a list of all groups and their pins, see the table 28 table. for duty cycles that are less than 100%, see table 29 . note that the v oh and v ol specifications have separate per-pin maximum current requirements (see table 19 on page 33 and table 20 on page 34 ). table 26. absolute maximum ratings parameter rating internal supply voltage (v ddint ) for adsp-bf523/adsp-bf525/adsp-bf527 processors C0.3 v to +1.26 v internal supply voltage (v ddint ) for adsp-bf522/adsp-bf524/adsp-bf526 processors C0.3 v to +1.47 v external (i/o) supply voltage (v ddext /v ddmem )C0.3 v to +3.8 v real-time clock supply voltage (v ddrtc ) C0.5 v to +3.8 v otp supply voltage (v ddotp ) C0.5 v to +3.0 v otp programming voltage (v ppotp ) 1 C0.5 v to +3.0 v otp programming voltage (v ppotp ) 2 C0.5 v to +7.1 v usb phy supply voltage (v ddusb ) C0.5 v to +3.8 v input voltage 3, 4, 5 C0.5 v to +3.8 v input voltage 3, 4, 6 C0.5 v to +5.5 v input voltage 3, 4, 7 C0.5 v to +5.25 v output voltage swing C0.5 v to v ddext /v ddmem + 0.5 v i oh /i ol current per pin group 3, 8 82 ma (max) storage temperature range C65c to +150c junction temperature while biased +110c 1 applies to otp memory reads and writes for adsp-bf523/adsp-bf525/ad sp-bf527 processors and to otp memory reads for adsp-bf522/a dsp-bf524/adsp-bf526 processors. 2 applies only to otp memory writes for ad sp-bf522/adsp-bf524/adsp -bf526 processors. 3 applies to 100% transient duty cycle. 4 applies only when v ddext is within specif ications. when v ddext is outside specificat ions, the range is v ddext 0.2 v. 5 for other duty cycles see table 27 . 6 applies to balls scl and sda. 7 applies to balls usb_dp, usb_dm, and usb_vbus. 8 for pin group information, see table 28 . for other duty cycles see table 29 . table 27. maximum duty cycle for input transient volt- age 1, 2 maximum duty cycle 3 v in min (v) 4 v in max (v) 6 100% C0.50 +3.80 40% C0.70 +4.00 25% C0.80 +4.10 15% C0.90 +4.20 10% C1.00 +4.30 1 applies to all signal balls with the exception of clkin, xtal, vr out / ext_wake1, scl, sda, usb_dp, usb_dm, and usb_vbus. 2 applies only when v ddext is within specifications. when v ddext is outside specifi- cations, the range is v ddext 0.2 v. 3 duty cycle refers to the percentage of time the signal exceeds the value for the 100% case. the is equivalent to the measured duration of a single instance of overshoot or undershoot as a percentage of the period of occurrence. 4 the individual values cannot be combined for analysis of a single instance of overshoot or undershoot. the worst case observed value must fall within one of the voltages specified, and the total duration of the overshoot or undershoot (exceeding the 100% case) must be less than or equal to the corresponding duty cycle. table 28. total current pin groups group pins in group 1 ph4, ph3, ph2, ph1, ph0, pf15, pf14, pf13 2 pf12, sda, scl, pf11, pf10, pf9, pf8, pf7 3 pf6, pf5, pf4, pf3, pf2, pf1, pf0, ppi_fs1 4 ppi_clk, pg15, pg14, pg13, pg12, pg11, pg10, pg9 5 pg8, pg7, pg6, pg5, pg4, bmode3, bmode2, bmode1
rev. d | page 38 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 when programming otp me mory on the adsp-bf522/ adsp-bf524/adsp-bf526 processors, the vppotp ball must be set to the write value specified in the operating conditions for adsp-bf522/adsp-bf524/adsp-bf526 processors on page 28 . there is a finite amount of cumulative time that the write voltage may be applied (d ependent on voltage and junc- tion temperature) to vppotp over the lifetime of the part. therefore, maximum otp memory programming time for the adsp-bf522/adsp-bf524/adsp-b f526 processors is shown in table 30 . the adsp-bf523/adsp-bf525/adsp-bf527 pro- cessors do not have a similar restriction. package information the information presented in figure 8 and table 31 provides details about the package branding for the adsp-bf52x proces- sors. for a complete listing of product availability, see ordering guide on page 88 . esd sensitivity 6 bmode0, pg3, pg2, pg1, pg0, tdi, tdo, emu 7tck, trst , tms 8 ph12, ph11, ph10, ph9, ph8, ph7, ph6, ph5 9 ph15, ph14, ph13, clkbuf, nmi , reset 10 data15, data14, data13, data12, data11, data10 11 data9, data8, data7, data6, data5, data4 12 data3, data2, data1, data0, addr19, addr18 13 addr17, addr16, addr15, addr14, addr13 14 addr12, addr11, addr10, addr9, addr8, addr7 15 addr6, addr5, addr4, addr3, addr2, addr1 16 abe1 , abe0 , sa10, swe , scas , sras 17 sms , scke, ardy, awe , are , aoe 18 ams3 , ams2 , ams1 , ams0 , clkout table 29. maximum duty cycle for i oh /i ol current per pin group maximum duty cycle rms current (ma) 100% 82 80% 92 60% 106 40% 130 25% 165 10% 261 table 30. maximum otp memory programming time for adsp-bf522/adsp-bf524/ adsp-bf526 processors temperature (t j ) v ppotp voltage (v) 25c 85c 105c 6.9 6000 sec 100 sec 25 sec 7.0 2400 sec 44 sec 12 sec 7.1 1000 sec 18 sec 4.5 sec table 28. total current pin groups (continued) group pins in group figure 8. product information on package table 31. package brand information 1 1 non automotive only. for branding in formation specific to automotive products, contact analog devices inc. brand key field description adsp-bf52x product name 2 2 see product names in the ordering guide on page 88 . t temperature range pp package type z lead free option ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliance designator yyww date code vvvvvv.x n.n tppzccc adsp-bf52x a #yyww country_of_origin b esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality.
rev. d | page 39 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 timing specifications specifications are subject to change without notice. clock and reset timing table 32 and figure 9 describe clock and reset operations. per the cclk and sclk timing specifications in table 12 to table 17 , combinations of clkin and clock multipliers must not select core/peripheral clocks in excess of the processor's maximum instruction rate. table 32. clock and reset timing parameter min max unit timing requirement s f ckin clkin frequency (commercial/ industrial models) 1, 2, 3, 4 12 50 mhz clkin frequency (automotive models) 1, 2, 3, 4 14 50 mhz t ckinl clkin low pulse 1 10 ns t ckinh clkin high pulse 1 10 ns t wrst reset asserted pulse width low 5 11 t ckin ns switching characteristic t bufdlay clkin to clkbuf delay 10 ns 1 applies to pll bypass mode and pll nonbypass mode. 2 combinations of the clkin frequency and the pl l clock multiplier must no t exceed the allowed f vco , f cclk , and f sclk settings discussed in table 12 on page 29 through table 14 on page 29 and table 15 on page 31 through table 17 on page 31 . 3 the t ckin period (see figure 9 ) equals 1/f ckin . 4 if the df bit in the pll_ctl register is set, the minimum f ckin specification is 24 mhz for commercial/industri al models and 28 mhz for automotive models. 5 applies after power-up se quence is complete. see table 33 and figure 10 for power-up reset timing. figure 9. clock and reset timing clkin t wrst t ckin t ckinl t ckinh t bufdlay t bufdlay reset clkbuf
rev. d | page 40 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 33. power-up reset timing parameter min max unit timing requirement t rst_in_pwr reset deasserted after the v ddint , v ddext , v ddrtc , v ddusb , v ddmem , v ddotp , and clkin pins are stable and within specification 3500 t ckin ns in figure 10 , v dd_supplies is v ddint , v ddext , v ddrtc , v ddusb , v ddmem , and v ddotp . figure 10. power -up reset timing reset t rst_in_pwr clkin v dd_supplies
rev. d | page 41 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 asynchronous memory read cycle timing table 34. asynchronous memory read cycle timing adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddmem 1.8 v nominal v ddmem 2.5 v or 3.3 v nominal v ddmem 1.8 v nominal v ddmem 2.5 v or 3.3 v nominal min max min max min max min max unit timing requirements t sdat data15C0 setup before clkout 2.1 2.1 2.1 2.1 ns t hdat data15C0 hold after clkout 1.2 0.8 0.9 0.8 ns t sardy ardy setup before clkout 4.0 4.0 4.0 4.0 ns t hardy ardy hold after clkout 0.2 0.2 0.2 0.2 ns switching characteristic s t do output delay after clkout 1 1 output balls include ams3C0 , abe1C0 , addr19C1, aoe , are . 6.0 6.0 6.0 6.0 ns t ho output hold after clkout 1 0.8 0.8 0.8 0.8 ns figure 11. asynchronous memory read cycle timing t hardy setup 2 cycles programmed read access 4 cycles access extended 3 cycles hold 1 cycle t do t ho t do t hardy t sardy t sdat t hdat t sardy clkout amsx abe1C0 addr19C1 aoe are ardy data 15C0 t ho
rev. d | page 42 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 asynchronous memory write cycle timing table 35. asynchronous memory write cycle timing adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddmem 1.8 v nominal v ddmem 2.5 v or 3.3 v nominal v ddmem 1.8 v nominal v ddmem 2.5 v or 3.3 v nominal min max min max min max min max unit timing requirements t sardy ardy setup before clkout 4.0 4.0 4.0 4.0 ns t hardy ardy hold after clkout 0.2 0.2 0.2 0.2 ns switching characteristic s t ddat data15C0 disable after clkout 6.0 6.0 6.0 6.0 ns t endat data15C0 enable after clkout 0.0 0.0 0.0 0.0 ns t do output delay after clkout 1 1 output balls include ams3C0 , abe1C0 , addr19C1, data15C0, awe . 6.0 6.0 6.0 6.0 ns t ho output hold after clkout 1 0.8 0.8 0.8 0.8 ns figure 12. asynchronous memory write cycle timing setup 2 cycles programmed write access 2 cycles access extend 1 cycle hold 1 cycle t do t ho clkout amsx abe1C0 addr19C1 awe ardy data 15C0 t sardy t sardy t ddat t endat t hardy t ho t do t hardy
rev. d | page 43 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 nand flash controller interface timing table 36 and figure 13 on page 44 through figure 17 on page 46 describe nand flash contro ller interface operations. table 36. nand flash controller interface timing v ddext 1.8 v nominal v ddext 2.5 v or 3.3 v nominal parameter min min unit write cycle switching characteristics t cwl nd_ce setup time to awe low 1.0 t sclk C 4 1.0 t sclk C 4 ns t ch nd_ce hold time from awe high 3.0 t sclk C 4 3.0 t sclk C 4 ns t clewl nd_cle setup time to awe low 0.0 0.0 ns t clh nd_cle hold time from awe high 2.5 t sclk C 4 2.5 t sclk C 4 ns t alewl nd_ale setup time to awe low 0.0 0.0 ns t alh nd_ale hold time from awe high 2.5 t sclk C 4 2.5 t sclk C 4 ns t wp 1 awe low to awe high (wr_dly +1.0) t sclk C 4 (wr_dly +1.0) t sclk C 4 ns t whwl awe high to awe low 4.0 t sclk C 4 4.0 t sclk C 4 ns t wc 1 awe low to awe low (wr_dly +5.0) t sclk C 4 (wr_dly +5.0) t sclk C 4 ns t dws 1 data setup time for a write access (wr_dly +1.5) t sclk C 4 (wr_dly +1.5) t sclk C 4 ns t dwh data hold time for a write access 2.5 t sclk C 4 2.5 t sclk C 4 ns read cycle switching characteristics t crl nd_ce setup time to are low 1.0 t sclk C 4 1.0 t sclk C 4 ns t crh nd_ce hold time from are high 3.0 t sclk C 4 3.0 t sclk C 4 ns t rp 1 are low to are high (rd_dly +1.0) t sclk C 4 (rd_dly +1.0) t sclk C 4 ns t rhrl are high to are low 4.0 t sclk C 4 4.0 t sclk C 4 ns t rc 1 are low to are low (rd_dly +5.0) t sclk C 4 (rd_dly +5.0) t sclk C 4 ns timing requirements (adsp-bf522/adsp-bf524/adsp-bf526) t drs data setup time for a read transaction 14.0 10.0 ns t drh data hold time for a read transaction 0.0 0.0 ns timing requirements (adsp-bf523/adsp-bf525/adsp-bf527) t drs data setup time for a read transaction 11.0 8.0 ns t drh data hold time for a read transaction 0.0 0.0 ns write followed by read switching characteristic t whrl awe high to are low 5.0 t sclk C 4 5.0 t sclk C 4 ns 1 wr_dly and rd_dly are defined in the nfc_ctl register.
rev. d | page 44 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 in figure 13 , nd_data is nd_d0Cd7. figure 13. nand flash controller interface timing command write cycle t clewl t alewl nd_data t ch t cwl t clh t alh t dwh nd_ce nd_cle nd_ale awe t wp t dws in figure 14 , nd_data is nd_d0Cd7. figure 14. nand flash controller interface timing address write cycle nd_data t wp t wp t alh t alh nd_ce nd_cle nd_ale awe t cwl t clewl t alewl t whwl t wc t dws t dwh t dws t dwh t alewl
rev. d | page 45 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 in figure 15 , nd_data is nd_d0Cd7. figure 15. nand flash controller interface timing data write operation nd_data nd_ce nd_cle nd_ale awe t cwl t clewl t alewl t wc t dws t dwh t dws t dwh t whwl t wp t wp in figure 16 , nd_data is nd_d0Cd7. figure 16. nand flash controller interface timing data read operation nd_data t rp nd_cle nd_ce nd_ale are t crl t crh t rp t rhrl t rc t drs t drh t drs t drh
rev. d | page 46 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 in figure 17 , nd_data is nd_d0Cd7. figure 17. nand flash controller interface timing write followed by read operation nd_data nd_cle t clwl t clewl t clh are awe t dws t dwh t drs t drh t whrl t wp t rp nd_ce
rev. d | page 47 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 sdram interface timing table 37. sdram interface timing for ad sp-bf522/adsp-bf524/adsp-bf526 processors parameter v ddmem 1.8v nominal v ddmem 2.5 v or 3.3v nominal min max min max unit timing requirement s t ssdat data setup before clkout 1.5 1.5 ns t hsdat data hold after clkout 1.3 0.8 ns switching characteristics t sclk clkout period 1 1 the t sclk value is the inverse of the f sclk specification discussed in table 14 and table 17 . package type and reduced supply voltages affect the best-case values listed here. 12.5 10 ns t sclkh clkout width high 5.0 4.0 ns t sclkl clkout width low 5.0 4.0 ns t dcad command, address, data delay after clkout 2 2 command balls include: sras , scas , swe , sdqm, sms , sa10, scke. 5.0 4.0 ns t hcad command, address, data hold after clkout 2 1.0 1.0 ns t dsdat data disable after clkout 5.5 5.0 ns t ensdat data enable after clkout 0.0 0.0 ns table 38. sdram interface timing for ad sp-bf523/adsp-bf525/adsp-bf527 processors parameter v ddmem 1.8v nominal v ddmem 2.5 v or 3.3v nominal min max min max unit timing requirement s t ssdat data setup before clkout 1.5 1.5 ns t hsdat data hold after clkout 1.0 0.8 ns switching characteristics t sclk clkout period 1 1 the t sclk value is the inverse of the f sclk specification discussed in table 14 and table 17 . package type and reduced supply voltages affect the best-case values listed here. 10 7.5 ns t sclkh clkout width high 2.5 2.5 ns t sclkl clkout width low 2.5 2.5 ns t dcad command, address, data delay after clkout 2 2 command balls include: sras , scas , swe , sdqm, sms , sa10, scke. 4.0 4.0 ns t hcad command, address, data hold after clkout 2 1.0 1.0 ns t dsdat data disable after clkout 5.0 4.0 ns t ensdat data enable after clkout 0.0 0.0 ns
rev. d | page 48 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 18. sdram interface timing t sclk clkout t sclkl t sclkh t ssdat t hsdat t ensdat t dcad t dsdat t hcad t dcad t hcad data (in) data (out) command, address (out) note: command = sras , scas , swe , sdqm, sms , sa10, scke.
rev. d | page 49 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 external dma request timing table 39 , table 40 , and figure 19 describe the external dma request operations. table 39. external dma request timing for adsp-bf522/adsp-bf524/adsp-bf526 processors 1 parameter v ddext /v ddmem 1.8 v nominal v ddext /v ddmem 2.5 v or 3.3 v nominal min max min max unit timing requirements t ds dmarx asserted to clkout high setup 9.0 6.0 ns t dh clkout high to dmarx deasserted hold time 0.0 0.0 ns t dmaract dmarx active pulse width 1.0 t sclk 1.0 t sclk ns t dmarinact dmarx inactive pulse width 1.75 t sclk 1.75 t sclk ns 1 because the external dma cont rol pins are part of the v ddext power domain and the clkout signal is part of the v ddmem power domain, systems in which v ddext and v ddmem are not equal may require level sh ifting logic for correct operation. table 40. external dma request timing for adsp-bf523/adsp-bf525/adsp-bf527 processors 1 parameter v ddext /v ddmem 1.8 v nominal v ddext /v ddmem 2.5 v or 3.3 v nominal min max min max unit timing requirements t ds dmarx asserted to clkout high setup 8.0 6.0 ns t dh clkout high to dmarx deasserted hold time 0.0 0.0 ns t dmaract dmarx active pulse width 1.0 t sclk 1.0 t sclk ns t dmarinact dmarx inactive pulse width 1.75 t sclk 1.75 t sclk ns 1 because the external dma cont rol pins are part of the v ddext power domain and the clkout signal is part of the v ddmem power domain, systems in which v ddext and v ddmem are not equal may require level sh ifting logic for correct operation. figure 19. external dma request timing clkout t ds dmar0/1 (active low) dmar0/1 (active high) t dmaract t dmarinact t dh
rev. d | page 50 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 parallel peripheral interface timing table 41 and figure 20 on page 51 , figure 24 on page 55 , and figure 27 on page 57 describe parallel peripheral interface operations. table 41. parallel peripheral interface timing for adsp-bf522/adsp-bf524/ adsp-bf526 processors parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3 v nominal min max min max unit timing requirements t pclkw ppi_clk width 1 6.4 6.4 ns t pclk ppi_clk period 1 25.0 20.0 ns timing requirements - gp input and frame capture modes t sfspe external frame sync setup before ppi_clk (nonsampling edge for rx, sampling edge for tx) 6.7 6.7 ns t hfspe external frame sync hold after ppi_clk 1.2 1.2 ns t sdrpe receive data setup before ppi_clk 4.1 3.5 ns t hdrpe receive data hold after ppi_clk 2.0 1.6 ns switching characteristics - gp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 8.0 8.0 ns t hofspe internal frame sync hold after ppi_clk 1.7 1.7 ns t ddtpe transmit data delay after ppi_clk 8.2 8.0 ns t hdtpe transmit data hold after ppi_clk 2.3 1.9 ns 1 ppi_clk frequency cannot exceed f sclk /2. table 42. parallel peripheral interface timing for adsp-bf523/adsp-bf525/ adsp-bf527 processors parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t pclkw ppi_clk width 1 6.0 6.0 ns t pclk ppi_clk period 1 20.0 15.0 ns timing requirements - gp input and frame capture modes t sfspe external frame sync setup before ppi_clk (nonsampling edge for rx, sampling edge for tx) 6.7 6.7 ns t hfspe external frame sync hold after ppi_clk 1.0 1.0 ns t sdrpe receive data setup before ppi_clk 3.5 3.5 ns t hdrpe receive data hold after ppi_clk 2.0 1.6 ns switching characteristics - gp output and frame capture modes t dfspe internal frame sync delay after ppi_clk 8.0 8.0 ns t hofspe internal frame sync hold after ppi_clk 1.7 1.7 ns t ddtpe transmit data delay after ppi_clk 8.0 8.0 ns t hdtpe transmit data hold after ppi_clk 2.3 1.9 ns 1 ppi_clk frequency cannot exceed f sclk /2.
rev. d | page 51 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 20. ppi gp rx mode with external frame sync timing figure 21. ppi gp tx mode with external frame sync timing figure 22. ppi gp rx mode with internal frame sync timing t pclk t sfspe data sampled / frame sync sampled data sampled / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t hdrpe t sdrpe t pclkw t hdtpe t sfspe data driven / frame sync sampled ppi_data ppi_clk ppi_fs1/2 t hfspe t ddtpe t pclk t pclkw t hdrpe t sdrpe t hofspe frame sync driven data sampled ppi_data ppi_clk ppi_fs1/2 t dfspe t pclk t pclkw
rev. d | page 52 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 23. ppi gp tx mode with internal frame sync timing t hofspe frame sync driven data driven ppi_data ppi_clk ppi_fs1/2 t dfspe t ddtpe t hdtpe t pclk t pclkw data driven
rev. d | page 53 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 serial ports table 43 through table 47 on page 57 and figure 24 on page 55 through figure 27 on page 57 describe serial port operations. table 43. serial portsexternal clock adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit timing requirements t sfse tfsx/rfsx setup before tsclkx rsclkx 1 3.0 3.0 3.0 3.0 ns t hfse tfsx/rfsx hold after tsclkx/rsclkx 1 3.0 3.0 3.0 3.0 ns t sdre receive data setup before rsclkx 1 3.0 3.0 3.0 3.0 ns t hdre receive data hold after rsclkx 1 3.5 3.0 3.5 3.0 ns t sclkew tsclkx/rsclkx width 7.0 4.5 7.0 4.5 ns t sclke tsclkx/rsclkx period 2.0 t sclk 2.0 t sclk 2.0 t sclk 2.0 t sclk ns t sudte start-up delay from sport enable to first external tfsx 2 4.0 t sclke 4.0 t sclke 4.0 t sclke 4.0 t sclke ns t sudre start-up delay from sport enable to first external rfsx 2 4.0 t sclke 4.0 t sclke 4.0 t sclke 4.0 t sclke ns switching characteristics t dfse tfsx/rfsx delay after tsclkx/rsclkx (internally generated tfsx/rfsx) 3 10.0 10.0 10.0 10.0 ns t hofse tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) 3 0.0 0.0 0.0 0.0 ns t ddte transmit data delay after tsclkx 3 10.0 10.0 10.0 10.0 ns t hdte transmit data hold after tsclkx 3 0.0 0.0 0.0 0.0 ns 1 referenced to sample edge. 2 verified in design but untested. 3 referenced to drive edge.
rev. d | page 54 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 44. serial portsinternal clock for adsp-bf522/adsp-bf524/adsp-bf526 processors parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclkx 1 11.0 9.6 ns t hfsi tfsx/rfsx hold after tsclkx/rsclkx 1 C1.5 C1.5 ns t sdri receive data setup before rsclkx 1 11.0 9.6 ns t hdri receive data hold after rsclkx 1 C1.5 C1.5 ns switching characteristics t sclkiw tsclkx/rsclkx width 10.0 8.0 ns t dfsi tfsx/rfsx delay after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 3.0 3.0 ns t hofsi tfsx/rfsx hold after tsclkx/rsclk x (internally generated tfsx/rfsx) 2 C2.0 C1.0 ns t ddti transmit data delay after tsclkx 2 3.0 3.0 ns t hdti transmit data hold after tsclkx 2 C1.8 C1.5 ns 1 referenced to sample edge. 2 referenced to drive edge. table 45. serial portsinternal clock for adsp-bf523/adsp-bf525/adsp-bf527 processors parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t sfsi tfsx/rfsx setup before tsclkx/rsclkx 1 11.0 9.6 ns t hfsi tfsx/rfsx hold after tsclkx/rsclkx 1 C1.5 C1.5 ns t sdri receive data setup before rsclkx 1 11.0 9.6 ns t hdri receive data hold after rsclkx 1 C1.5 C1.5 ns switching characteristics t sclkiw tsclkx/rsclkx width 4.5 4.5 ns t dfsi tfsx/rfsx delay after tsclkx/rsclkx (internally generated tfsx/rfsx) 2 3.0 3.0 ns t hofsi tfsx/rfsx hold after tsclkx/rsclkx (internally generated tfsx/rfsx) 2 C1.0 C1.0 ns t ddti transmit data delay after tsclkx 2 3.0 3.0 ns t hdti transmit data hold after tsclkx 2 C1.8 C1.5 ns 1 referenced to sample edge. 2 referenced to drive edge.
rev. d | page 55 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 24. serial ports figure 25. serial port start up with external clock and frame sync t sdri rsclkx drx drive edge t hdri t sfsi t hfsi t dfsi t h ofsi t sclkiw data receiveinternal clock t sdre data receiveexternal clock rsclkx drx t hdre t sfse t hfse t dfse t sclkew t hofse t ddti t hdti tsclkx tfsx (input) dtx t sfsi t hfsi t sclkiw t dfsi t hofsi data transmitinternal clock t ddte t hdte tsclkx dtx t sfse t dfse t sclkew t hofse data transmitexternal clock sample edge drive edge sample edge drive edge sample edge drive edge sample edge t sclke t sclke t hfse tfsx (output) tfsx (input) tfsx (output) rfsx (input) rfsx (output) rfsx (input) rfsx (output) tsclkx (input) tfsx (input) rfsx (input) rsclkx (input) t sudte t sudre first tsclkx/rsclkx edge after sport enabled
rev. d | page 56 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 46. serial portsenable and three-state adsp-bf522/adsp-bf524/adsp-bf526 adsp-bf523/adsp-bf525/adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit switching characteristics t dtene data enable delay from external tsclkx 1 0.0 0.0 0.0 0.0 ns t ddtte data disable delay from external tsclkx 1 t sclk +1 t sclk +1 t sclk +1 t sclk +1 ns t dteni data enable delay from internal tsclkx 1 C2.0 C2.0 C2.0 C2.0 ns t ddtti data disable delay from internal tsclkx 1 t sclk +1 t sclk +1 t sclk +1 t sclk +1 ns 1 referenced to drive edge. figure 26. serial ports enable and three-state tsclkx dtx drive edge t ddtte/i t dtene/i drive edge
rev. d | page 57 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 47. serial ports external late frame sync adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit switching characteristics t ddtlfse data delay from late external tfsx or external rfsx in multi-channel mode with mfd = 0 1, 2 12.0 10.0 12.0 10.0 ns t dtenlfse data enable from external rfsx in multi- channel mode with mfd = 0 1, 2 0.0 0.0 0.0 0.0 ns 1 when in multi-channel mode, tfsx enable and tfsx valid follow t dtenlfse and t ddtlfse . 2 if external rfsx/tfsx setu p to rsclkx/tsclkx > t sclke /2 then t ddtte/i and t dtene/i apply, otherwise t ddtlfse and t dtenlfse apply. figure 27. serial ports external late frame sync rsclkx rfsx dtx drive edge drive edge sample edge external rfsx in multi-channel mode 1st bit t dtenlfse t ddtlfse tsclkx tfsx dtx drive edge drive edge sample edge late external tfsx 1st bit t ddtlfse
rev. d | page 58 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 serial peripheral interface (spi) portmaster timing table 48 and figure 28 describe spi port master operations. table 48. serial peripheral interface (spi) portmaster timing adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit timing requirements t sspidm data input valid to sck edge (data input setup) 11.6 9.6 11.6 9.6 ns t hspidm sck sampling edge to data input invalid C1.5 C1.5 C1.5 C1.5 ns switching characteristics t sdscim spiselx low to first sck edge 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spichm serial clock high period 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spiclm serial clock low period 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk C1.5 4 t sclk C1.5 4 t sclk C1.5 4 t sclk C1.5 ns t hdsm last sck edge to spiselx high 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spitdm sequential transfer delay 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t ddspidm sck edge to data out valid (data out delay) 6666ns t hdspidm sck edge to data out invalid (data out hold) C1.0 C1.0 C1.0 C1.0 ns figure 28. serial peripheral interface (spi) portmaster timing t sdscim t spiclk t hdsm t spitdm t spiclm t spichm t hdspidm t hspidm t sspidm spixsely (output) spixsck (output) spixmosi (output) spixmiso (input) spixmosi (output) spixmiso (input) cpha = 1 cpha = 0 t ddspidm t hspidm t sspidm t hdspidm t ddspidm
rev. d | page 59 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 serial peripheral interface (spi) portslave timing table 49 and figure 29 describe spi port slave operations. table 49. serial peripheral interface (spi) portslave timing adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit timing requirements t spichs serial clock high period 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spicls serial clock low period 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spiclk serial clock period 4 t sclk C1.5 4 t sclk C1.5 4 t sclk C1.5 4 t sclk C1.5 ns t hds last sck edge to spiss not asserted 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t spitds sequential transfer delay 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t sdsci spiss assertion to first sck edge 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 2 t sclk C1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 1.6 1.6 1.6 ns t hspid sck sampling edge to data input invalid 2.0 1.6 1.6 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 12.0 0 10.3 0 12.0 0 10.3 ns t dsdhi spiss deassertion to data high impedance 0 11.0 0 8.5 0 8.5 0 8 ns t ddspid sck edge to data out valid (data out delay) 10 10 10 10 ns t hdspid sck edge to data out invalid (data out hold) 0 0 0 0 ns figure 29. serial peripheral interface (spi) portslave timing t spiclk t hds t spitds t sdsci t spicls t spichs t dsoe t ddspid t ddspid t dsdhi t hdspid t sspid t dsdhi t hdspid t dsoe t hspid t sspid t ddspid spixss (input) spixsck (input) spixmiso (output) spixmosi (input) spixmiso (output) spixmosi (input) cpha = 1 cpha = 0 t hspid
rev. d | page 60 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 universal serial bus (usb) on-the-goreceive and transmit timing table 50 describes the usb on-the-go receive and transmit operations. table 50. usb on-the-goreceive and transmit timing adsp-bf522/adsp-bf524/adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit timing requirements f usbs usb_xi frequency 12 33.3 12 33.3 9 33.3 9 33.3 mhz fs usb usb_xi clock frequency stability C50 +50 C50 +50 C50 +50 C50 +50 ppm
rev. d | page 61 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 universal asynchronous receiver-transmitter (uart) portsreceive and transmit timing for information on the uart po rt receive and transmit opera- tions, see the adsp-bf52x hardware reference manual . general-purpose port timing table 51 and figure 30 describe general-purpose port operations. table 51. general-purpose port timing for adsp-bf522/adsp-bf524/adsp-bf526 processors parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirement t wfi general-purpose port ball input pulse width t sclk + 1 t sclk + 1 ns switching characteristic t gpod general-purpose port ball output delay from clkout low 0 11.0 0 8.2 ns table 52. general-purpose port timing for adsp-bf523/adsp-bf525/adsp-bf527 processors parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirement t wfi general-purpose port ball input pulse width t sclk + 1 t sclk + 1 ns switching characteristic t gpod general-purpose port ball output delay from clkout low 0 8.2 0 6.5 ns figure 30. general-purpose port timing clkout gpio output gpio input t wfi t gpod
rev. d | page 62 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 timer cycle timing table 53 and figure 31 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of (f sclk /2) mhz. table 53. timer cycle timing adsp-bf522/adsp-bf524/adsp-bf526 adsp-bf523/adsp-bf525/adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal minmaxminmaxminmaxminmaxunit timing requirements t wl timer pulse width input low (measured in sclk cycles) 1 t sclk t sclk t sclk t sclk ns t wh timer pulse width input high (measured in sclk cycles) 1 t sclk t sclk t sclk t sclk ns t tis timer input setup time before clkout low 2 10 7 8.1 6.2 ns t tih timer input hold time after clkout low 2 C2 C2 C2 C2 ns switching characteristics t hto timer pulse width output (measured in sclk cycles) t sclk C1.5 (2 32 C 1)t sclk t sclk C 1 (2 32 C 1)t sclk t sclk C 1 (2 32 C 1)t sclk t sclk C 1 (2 32 C 1)t sclk ns t tod timer output update delay after clkout high 6666ns 1 the minimum pulse widths apply for tmrx sign als in width capture and external clock mode s. they also apply to the pf15 or ppi_c lk signals in pwm output mode. 2 either a valid setup and hold time or a valid pulse width is suff icient. there is no need to resynchronize programmable flag i nputs. figure 31. timer cycle timing clkout tmrx output tmrx input t tis t tih t wh ,t wl t tod t hto
rev. d | page 63 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 timer clock timing table 54 and figure 32 describe timer clock timing. up/down counter/rotary encoder timing table 54. timer clock timing parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit switching characteristic t todp timer output update delay after ppi_clk high 12.0 12.0 ns figure 32. timer clock timing table 55. up/down counter/rotary encoder timing parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t wcount up/down counter/rotary encoder input pulse width t sclk + 1 t sclk + 1 ns t cis counter input setup time before clkout high 1 1 either a valid setup and hold time or a valid pulse width is su fficient. there is no need to resynchronize counter inputs. 9.0 7.0 ns t cih counter input hold time after clkout high 1 00ns figure 33. up/down counter/rotary encoder timing ppi_clk tmrx output t todp clkout cud/cdg/czm t cis t cih t wcount
rev. d | page 64 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 hostdp a/c timing- host read cycle table 56 describes the hostdp a/c host read cycle timing requirements. table 56. host read cycle timing requirements adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit timing requirements t sadrdl host_addr and host_ce setup before host_rd falling edge 4444ns t hadrdh host_addr and host_ce hold after host_rd rising edge 2.5 2.5 2.5 2.5 ns t rdwl host_rd pulse width low (ack mode) t drdyrdl + t rdyprd + t drdhrdy t drdyrdl + t rdyprd + t drdhrdy t drdyrdl + t rdyprd + t drdhrdy t drdyrdl + t rdyprd + t drdhrdy ns t rdwl host_rd pulse width low (int mode) 1.5 t sclk + 8.7 1.5 t sclk + 8.7 1.5 t sclk + 8.7 1.5 t sclk + 8.7 ns t rdwh host_rd pulse width high or time between host_rd rising edge and host_wr falling edge 2 t sclk 2 t sclk 2 t sclk 2 t sclk ns t drdhrdy host_rd rising edge delay after host_ack rising edge (ack mode) 2.02.000ns switching characteristics t sdatrdy data valid prior host_ack rising edge (ack mode) 4.5 3.5 4.5 3.5 ns t drdyrdl host_ack falling edge after host_ce (ack mode) 12.5 11.25 11.25 11.25 ns t rdyprd host_ack low pulse-width for read access (ack mode) nm 1 nm 1 nm 1 nm 1 ns t ddarwh data disable after host_rd 11.0 9.0 9.0 9.0 ns t acc data valid after host_rd falling edge (int mode) 1.5 t sclk 1.5 t sclk 1.5 t sclk 1.5 t sclk ns t hdarwh data hold after host_rd rising edge 1.0 1.0 1.0 1.0 ns 1 nm (not measured) this parameter is based on t sclk . it is not measured because the number of sclk cycles for which host_ack is low depends on the host dma fifo status and is system design dependent.
rev. d | page 65 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 in figure 34 , host_data is host_d0Cd15. figure 34. hostdp a/c- host read cycle host_rd host_ack host_data t sadrdl t hadrdh t drdhrdy t hdarwh t rdyprd t drdyrdl t sdatrdy host_addr host_ce t rdwl t rdwh t acc t ddarwh
rev. d | page 66 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 hostdp a/c timing- host write cycle table 57 describes the hostdp a/c host write cycle timing requirements. table 57. host write cycle timing requirements adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit timing requirements t sadwrl host_addr/host_ce setup before host_wr falling edge 4444ns t hadwrh host_addr/host_ce hold after host_wr rising edge 2.5 2.5 2.5 2.5 ns t wrwl host_wr pulse width low (ack mode) t drdywrl + t rdyprd + t dwrhrdy t drdywrl + t rdyprd + t dwrhrdy t drdywrl + t rdyprd + t dwrhrdy t drdywrl + t rdyprd + t dwrhrdy ns host_wr pulse width low (int mode) 1.5 t sclk + 8.7 1.5 t sclk + 8.7 1.5 t sclk + 8.7 1.5 t sclk + 8.7 ns t wrwh host_wr pulse width high or time between host_wr rising edge and host_rd falling edge 2 t sclk 2 t sclk 2 t sclk 2 t sclk ns t dwrhrdy host_wr rising edge delay after host_ack rising edge (ack mode) 2.02.000ns t hdatwh data hold after host_wr rising edge 2.5 2.5 2.5 2.5 ns t sdatwh data setup before host_wr rising edge 3.5 2.5 2.5 2.5 ns switching characteristics t drdywrl host_ack falling edge after host_ce asserted (ack mode) 12.5 11.5 11.5 11.5 ns t rdypwr host_ack low pulse-width for write access (ack mode) nm 1 nm 1 nm 1 nm 1 ns 1 nm (not measured) this parameter is based on t sclk . it is not measured because the number of sclk cycles for which host_ack is low depends on the host dma fifo status and is system design dependent.
rev. d | page 67 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 in figure 35 , host_data is host_d0Cd15. figure 35. hostdp a/c- host write cycle host_wr host_ack host_data t sadwrl t hadwrh t dwrhrdy t rdypwr t drdywrl t sdatwh host_addr host_ce t wrwl t wrwh t hdatwh
rev. d | page 68 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 10/100 ethernet mac controller timing table 58 through table 63 and figure 36 through figure 41 describe the 10/100 ethernet mac cont roller operations. table 58. 10/100 ethernet mac controll er timing: mii receive signal parameter 1 v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t erxclkf erxclk frequency (f sclk = sclk frequency) none 25 + 1% none 25 + 1% mhz t erxclkw erxclk width (t erxclk = erxclk period) t erxclk 40% t erxclk 60% t erxclk 35% t erxclk 65% ns t erxclkis rx input valid to erxclk rising edge (data in setup) 7.5 7.5 ns t erxclkih erxclk rising edge to rx input invalid (data in hold) 7.5 7.5 ns 1 mii inputs synchronous to erxclk are erxd3C0, erxdv, and erxer. figure 36. 10/100 ethernet mac controller timing: mii receive signal table 59. 10/100 ethernet mac controll er timing: mii transmit signal parameter 1 v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit switching characteristics t etxclkf etxclk frequency (f sclk = sclk frequency) none 25 + 1% none 25 + 1% mhz t etxclkw etxclk width (t etxclk = etxclk period) t etxclk 40% t etxclk 60% t etxclk 35% t etxclk 65% ns t etxclkov etxclk rising edge to tx output valid (data out valid) 20 20 ns t etxclkoh etxclk rising edge to tx output invalid (data out hold) 00ns 1 mii outputs synchronous to etxclk are etxd3C0. figure 37. 10/100 ethernet mac controller timing: mii transmit signal t erxclkis t erxclkih erxd3C0 erxdv erxer erx_clk t erxclkw t erxclk t etxclkoh etxd3C0 etxen miitxclk t etxclk t etxclkov t etxclkw
rev. d | page 69 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 60. 10/100 ethernet mac controll er timing: rmii receive signal parameter 1 v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t erefclkf ref_clk frequency (f sclk = sclk frequency) none 50 + 1% none 50 + 1% mhz t erefclkw eref_clk width (t erefclk = erefclk period) t erefclk 40% t erefclk 60% t erefclk 35% t erefclk 65% ns t erefclkis rx input valid to rmii ref_clk rising edge (data in setup) 44ns t erefclkih rmii ref_clk rising edge to rx input invalid (data in hold) 22ns 1 rmii inputs synchronous to rmii ref_clk are erxd1C0, rmii crs_dv, and erxer. figure 38. 10/100 ethernet mac controller timing: rmii receive signal table 61. 10/100 ethernet mac controller timing: rmii transmit signal adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter 1 v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit switching characteristics t erefclkov rmii ref_clk rising edge to tx output valid (data out valid) 8.1 8.1 7.5 7.5 ns t erefclkoh rmii ref_clk rising edge to tx output invalid (data out hold) 22 22 ns 1 rmii outputs synchronous to rmii ref_clk are etxd1C0. figure 39. 10/100 ethernet mac controller timing: rmii transmit signal t refclkis t refclkih erxd1C0 erxdv erxer rmii_ref_clk t refclkw t refclk t refclkov t refclkoh rmii_ref_clk etxd1C0 etxen t refclk
rev. d | page 70 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 62. 10/100 ethernet mac controller timing: mii/rmii asynchronous signal parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t ecolh col pulse width high 1 t etxclk 1.5 t erxclk 1.5 t etxclk 1.5 t erxclk 1.5 ns t ecoll col pulse width low 1 t etxclk 1.5 t erxclk 1.5 t etxclk 1.5 t erxclk 1.5 ns t ecrsh crs pulse width high 2 t etxclk 1.5 t etxclk 1.5 ns t ecrsl crs pulse width low 2 t etxclk 1.5 t etxclk 1.5 ns 1 mii/rmii asynchronous signals are col and crs. these signals are a pplicable in both mii and rmii modes. the asynchronous col in put is synchronized separately to both the etxclk and the erxclk, and the col input must have a mini mum pulse width high or low at least 1.5 times the period of the slower of the two clocks. 2 the asynchronous crs input is synchronized to the etxclk, and th e crs input must have a minimum pulse width high or low at leas t 1.5 times the period of etxclk. figure 40. 10/100 ethernet mac controller timing: asynchronous signal table 63. 10/100 ethernet mac controller timing: mii station management adsp-bf522/adsp-bf524/ adsp-bf526 adsp-bf523/adsp-bf525/ adsp-bf527 parameter 1 v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max min max min max unit timing requirements t mdios mdio input valid to mdc rising edge (setup) 11.5 11.5 10 10 ns t mdcih mdc rising edge to mdio input invalid (hold) 11.5 11.5 10 10 ns switching characteristics t mdcov mdc falling edge to mdio output valid 25 25 25 25 ns t mdcoh mdc falling edge to mdio output invalid (hold) C1 C1 C1 C1 ns 1 mdc/mdio is a 2-wire serial bidirectional port for controlling one or more external phys. mdc is an output clock whose minimum period is programmable as a multiple of the system clock sclk. mdio is a bidirectional data line. miicrs, col t ecrsh t ecolh t ecrsl t ecoll
rev. d | page 71 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 41. 10/100 ethernet mac contro ller timing: mii station management mdio (input) mdio (output) mdc (output) t mdios t mdcoh t mdcih t mdcov
rev. d | page 72 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 jtag test and emulation port timing table 64 and figure 42 describe jtag port operations. table 64. jtag port timing parameter v ddext 1.8v nominal v ddext 2.5 v or 3.3v nominal min max min max unit timing requirements t tck tck period 20 20 ns t stap tdi, tms setup before tck high 4 4 ns t htap tdi, tms hold after tck high 4 4 ns t ssys system inputs setup before tck high 1 12 12 ns t hsys system inputs hold after tck high 1 55ns t trstw trst pulse width 2 (measured in tck cycles) 4 4 tck switching characteristics t dtdo tdo delay from tck low 10 10 ns t dsys system outputs delay after tck low 3 12 12 ns 1 system inputs = data15C0, ardy, scl, sda, pf15C0, pg15C0, ph15C0, reset , nmi , bmode3C0. 2 50 mhz maximum. 3 system outputs = data15C0, addr19C1, abe1C0 , aoe , are , awe , ams3C0 , sras , scas , swe , scke, clkout, sa10, sms , scl, sda, pf15C0, pg15C0, ph15C0. figure 42. jtag port timing tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. d | page 73 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 output drive currents figure 43 through figure 57 show typical current-voltage char- acteristics for the output driver s of the adsp-bf52x processors. the curves represent the current drive capability of the output drivers. see table 10 on page 23 for information about which driver type corresponds to a particular ball. figure 43. driver type a current (3.3v v ddext /v ddmem ) figure 44. driver type a current (2.5v v ddext /v ddmem ) figure 45. driver type a current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 200 120 80 C200 C120 C40 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C80 C160 40 160 v ddext = 3.0v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 160 120 40 C160 C120 C40 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 80 C80 v ddext = 2.25v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 80 60 40 C80 C60 C20 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 105 c figure 46. driver type b current (3.3v v ddext /v ddmem ) figure 47. driver type b current (2.5v v ddext /v ddmem ) figure 48. driver type b current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 240 120 80 C240 C120 C40 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C80 C200 40 160 v ddext = 3.0v @ 105 c C160 200 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 160 120 40 C200 C160 C40 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 80 C80 v ddext = 2.25v @ 105 c C120 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 80 60 40 C100 C60 C20 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 105 c C80
rev. d | page 74 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 49. driver type c current (3.3v v ddext /v ddmem ) figure 50. drive type c current (2.5v v ddext /v ddmem ) figure 51. driver type c current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 100 60 40 C100 C60 C20 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C40 C80 20 80 v ddext = 3.0v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 80 60 20 C80 C60 C20 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 40 C40 v ddext = 2.25v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 40 30 20 C40 C30 C10 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C20 10 v ddext = 1.7v @ 105 c figure 52. driver type d current (3.3v v ddext /v ddmem ) figure 53. driver type d current (2.5v v ddext /v ddmem ) figure 54. driver type d current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 160 120 80 C160 C40 v ol v oh v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C80 C120 40 v ddext = 3.0v @ 105 c 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 120 100 40 C120 C100 C40 v ol v oh v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 80 C60 v ddext = 2.25v @ 105 c C80 C20 20 60 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 60 40 C60 C20 v ol v oh v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C40 20 v ddext = 1.7v @ 105 c
rev. d | page 75 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 test conditions all timing requirements appearing in this data sheet were measured under the conditions described in this section. figure 58 shows the measurement po int for ac measurements (except output enable/disable ). the measurement point v meas is v ddext /2 or v ddmem /2 for v ddext /v ddmem (nominal) = 1.8 v/ 2.5 v/3.3 v. output enable time measurement output balls are considered to be enabled when they have made a transition from a high impedanc e state to the po int when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown on the right side of figure 59 . the time t ena_measured is the interval from when the reference signal switches to when the output voltage reaches v trip (high) or v trip (low). for v ddext /v ddmem (nominal) = 1.8 v, v trip (high) is 1.05 v, and v trip (low) is 0.75 v. for v ddext /v ddmem (nominal) = 2.5 v, v trip (high) is 1.5 v and v trip (low) is 1.0 v. for v ddext /v ddmem (nominal) = 3.3 v, v trip (high) is 1.9 v, and v trip (low) is 1.4 v. time t trip is the interval from when the out- put starts driving to when the output reaches the v trip (high) or v trip (low) trip voltage. time t ena is calculated as sh own in the equation: if multiple balls (such as the da ta bus) are enabled, the measure- ment value is that of the first ball to start driving. figure 55. driver type e current (3.3v v ddext /v ddmem ) figure 56. driver type e current (2.5v v ddext /v ddmem ) figure 57. driver type e current (1.8v v ddext /v ddmem ) 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 60 30 20 C60 C30 C10 v ol v ddext = 3.6v @ C 40 c v ddext = 3.3v @ 25 c C20 C40 10 40 v ddext = 3.0v @ 105 c 50 C50 3.0 3.5 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 2.0 2.5 40 30 10 C40 C30 C10 v ol v ddext = 2.75v @ C 40 c v ddext = 2.5v @ 25 c 20 C20 v ddext = 2.25v @ 105 c 3.5 0 source current (ma) source voltage (v) 0 0.5 1.0 1.5 20 15 10 C20 C15 C5 v ol v ddext = 1.9v @ C 40 c v ddext = 1.8v @ 25 c C10 5 v ddext = 1.7v @ 105 c 3.0 2.5 2.0 figure 58. votage reference leves for ac measurements (except output enae/disae) figure 59. output enae/disae input or output v meas v meas reference signal t dis output starts driving v oh (measured) v v ol (measured) + v t dis_measured v oh (measured) v ol (measured) v trip (high) v oh (measured ) v ol (measured) high impedance state output stops driving t ena t decay t ena_measured t trip v trip (low) t ena t ena_measured t trip ? =
rev. d | page 76 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 output disable time measurement output balls are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the output disable time t dis is the difference between t dis_measured and t decay as shown on the left side of figure 59 . the time for the voltage on the bus to decay by v is dependent on the capacitive load c l and the load current i l . this decay time can be approximated by the equation: the time t decay is calculated with test loads c l and i l , and with ? v equal to 0.25 v for v ddext /v ddmem (nominal) = 2.5 v/3.3 v and 0.15 v for v ddext /v ddmem (nominal) = 1.8v. the time t dis_measured is the interval from when the reference signal switches, to when the output voltage decays v from the measured output high or output low voltage. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the processors output voltage and the input threshold for the device requiring the hold time. c l is the total bus capacitance (per data line), and i l is the total leak- age or three-state current (per data line). the hold time will be t decay plus the various output disa ble times as specified in the timing specifications on page 39 (for example t dsdat for an sdram write cycle as shown in sdram interface timing on page 47 ). capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all balls (see figure 60 ). v load is equal to (v ddext /v ddmem ) /2. the graphs of figure 61 through figure 72 show how output rise time varies with capacitance. the delay and hold specifications given should be derated by a factor derived from these figure s. the graphs in these figures may not be linear outside the ranges shown. t dis t dis_measured t decay ? = t decay c l v ? ?? i l ? = figure 60. equivalent device loading for ac measurements (includes all fixtures) figure 61. driver type a typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) t1 zo = 50 (impedance) td = 4.04 1.18 ns 2pf tester pin electronics 50 0.5pf 70 400 45 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td) is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. v load dut output 50 6 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 12 10 0 2 4 8 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c
rev. d | page 77 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 62. driver type a typical rise and fall times (10%C90%) vs. load capacitance (2.5v v ddext /v ddmem ) figure 63. driver type a typical rise and fall times (10%C90%) vs. load capacitance (3.3v v ddext /v ddmem ) figure 64. driver type b typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) 4 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 8 6 0 1 2 5 200 t rise t fall 3 7 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 3 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 6 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 4 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 9 7 0 1 3 6 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c 2 5 8 figure 65. driver type b typica rise and fa times (10%C90%) vs. load capacitance (2.5v v ddext /v ddmem ) figure 66. driver type b typica rise and fa times (10%C90%) vs. load capacitance (3.3v v ddext /v ddmem ) figure 67. driver type c typica rise and fa times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) 4 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 7 6 0 1 2 5 200 t rise t fall 3 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 3 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 6 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 15 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 25 20 0 5 10 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c
rev. d | page 78 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 68. driver type c typical rise and fall times (10%C90%) vs. load capacitance (2.5v v ddext /v ddmem ) figure 69. driver type c typical rise and fall times (10%C90%) vs. load capacitance (3.3v v ddext /v ddmem ) figure 70. driver type d typical rise and fall times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) 8 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 16 12 0 2 4 10 200 t rise t fall 6 14 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 6 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 14 12 0 2 4 8 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 10 6 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 14 10 0 2 4 8 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c 12 figure 71. driver type d typica rise and fa times (10%C90%) vs. load capacitance (2.5v v ddext /v ddmem ) figure 72. driver type d typica rise and fa times (10%C90%) vs. load capacitance (3.3v v ddext /v ddmem ) figure 73. driver type g typica rise and fa times (10%C90%) vs. load capacitance (1.8v v ddext /v ddmem ) 4 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 10 6 0 1 2 5 200 t rise t fall 3 7 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 8 9 3 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 8 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 6 7 4 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 9 6 0 1 2 5 200 t rise t fall t rise = 1.8v @ 25 c t fall = 1.8v @ 25 c 8 3 7
rev. d | page 79 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 environmental conditions to determine the junction te mperature on the application printed circuit board use: where: t j = junction temperature (c) t case = case temperature (c) measured by customer at top center of package. ? jt = from table 66 p d = power dissipation for a description, see total power dissipation on page 35 . values of ? ja are provided for packag e comparison and printed circuit board design considerations. ? ja can be used for a first order approximation of t j by the equation: where: t a = ambient temperature (c) values of ? jc are provided for packag e comparison and printed circuit board design considerations when an external heat sink is required. values of ? jb are provided for package comparison and printed circuit board design considerations. in table 66 , airflow measurements comply with jedec stan- dards jesd51-2 and jesd51-6, and the junction-to-board measurement complies with je sd51-8. the junction-to-case measurement complies with mil-std-883 (method 1012.1). all measurements use a 2s2p jedec test board. figure 74. driver type g typical ri se and fall times (10%C90%) vs. load capacitance (2.5v v ddext /v ddmem ) figure 75. driver type g typical ri se and fall times (10%C90%) vs. load capacitance (3.3v v ddext /v ddmem ) 4 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 6 0 1 2 5 200 t rise t fall 3 7 t rise = 2.5v @ 25 c t fall = 2.5v @ 25 c 8 9 3 rise and fall time (10% to 90%) load capacitance (pf) 0 50 100 150 9 5 0 1 2 4 200 t rise t fall t rise = 3.3v @ 25 c t fall = 3.3v @ 25 c 6 8 7 t j t case ? jt p d ? ?? + = table 65. thermal characteri stics for bc-208-1 package parameter condition typical unit ? ja 0 linear m/s air flow 23.20 c/w ? jma 1 linear m/s air flow 20.20 c/w ? jma 2 linear m/s air flow 19.20 c/w ? jb 13.05 c/w ? jc 6.92 c/w ? jt 0 linear m/s air flow 0.18 c/w ? jt 1 linear m/s air flow 0.27 c/w ? jt 2 linear m/s air flow 0.32 c/w table 66. thermal characteri stics for bc-289-2 package parameter condition typical unit ? ja 0 linear m/s air flow 34.5 c/w ? jma 1 linear m/s air flow 31.1 c/w ? jma 2 linear m/s air flow 29.8 c/w ? jb 20.3 c/w ? jc 8.8 c/w ? jt 0 linear m/s air flow 0.24 c/w ? jt 1 linear m/s air flow 0.44 c/w ? jt 2 linear m/s air flow 0.53 c/w t j t a ? ja p d ? ?? + =
rev. d | page 80 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 289-ball csp_bga ball assignment table 67 lists the csp_bga balls by signal mnemonic. table 68 on page 81 lists the csp_bga by ball number. table 67. 289-ball csp_bga ball assign ment (alphabetica lly by signal) signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. abe0 /sdqm0 ab9 data6 t2 gnd m10 nc d23 ph0 a11 usb_xo aa23 v ddint r8 abe1 /sdqm1 ac9 data7 t1 gnd m11 nc e22 ph1 a12 v ddext g7 v ddint r16 addr1 ab8 data8 r1 gnd m12 nc e23 ph2 a13 v ddext g8 v ddint t8 addr2 ac8 data9 p1 gnd m13 nc f22 ph3 b14 v ddext g9 v ddint t9 addr3 ab7 data10 p2 gnd m14 nc f23 ph4 a14 v ddext g10 v ddint t10 addr4 ac7 data11 r2 gnd m15 nc g22 ph5 k23 v ddext g11 v ddint t11 addr5 ac6 data12 n1 gnd n9 nc h23 ph6 k22 v ddext g12 v ddint t12 addr6 ab6 data13 n2 gnd n10 nc j23 ph7 l23 v ddext g13 v ddint t13 addr7 ab4 data14 m2 gnd n11 nmi u22 ph8 l22 v ddext g14 v ddint t14 addr8 ab5 data15 m1 gnd n12 vppotp ab11 ph9 t23 v ddext g15 v ddint t15 addr9 ac5 emu j2 gnd n13 pf0 a7 ph10 m22 v ddext h7 v ddint t16 addr10 ac4 ext_wake0 ac19 gnd n14 pf1 b8 ph11 r22 v ddext j17 v ddmem j7 addr11 ab3 gnd a1 gnd n15 pf2 a8 ph12 m23 v ddext k17 v ddmem k7 addr12 ac3 gnd a23 gnd p9 pf3 b9 ph13 n22 v ddext l17 v ddmem l7 addr13 ab2 gnd b6 gnd p10 pf4 b11 ph14 n23 v ddext m17 v ddmem m7 addr14 ac2 gnd 1 g16 gnd p11 pf5 b10 ph15 p22 v ddext n17 v ddmem n7 addr15 aa2 gnd g17 gnd p12 pf6 b12 ppi_clk/tmrclk a6 v ddext p17 v ddmem p7 addr16 w2 gnd 1 h17 gnd p13 pf7 b13 ppi_fs1/tmr0 b7 v ddext r17 v ddmem r7 addr17 y2 gnd h22 gnd p14 pf8 b16 reset v22 v ddext t17 v ddmem t7 addr18 aa1 gnd 1 j22 gnd p15 pf9 a20 rtxi u23 v ddext u17 v ddmem u7 addr19 ab1 gnd j9 gnd r9 pf10 b15 rtxo v23 v ddint b5 v ddmem u8 ams0 ac17 gnd j10 gnd r10 pf11 b17 sa10 ac10 v ddint h8 v ddmem u9 ams1 ab16 gnd j11 gnd r11 pf12 b18 scas ac11 v ddint h9 v ddmem u10 ams2 ac16 gnd j12 gnd r12 pf13 b19 scke ab13 v ddint h10 v ddmem u11 ams3 ab15 gnd j13 gnd r13 pf14 a9 scl b22 v ddint h11 v ddmem u12 aoe ac15 gnd j14 gnd r14 pf15 a10 sda c22 v ddint h12 v ddmem u13 ardy ac14 gnd j15 gnd r15 pg0 h2 sms ac13 v ddint h13 v ddmem u14 are ab17 gnd k9 gnd t22 pg1 g1 sras ab12 v ddint h14 v ddmem u15 awe ab14 gnd k10 gnd ac1 pg2 h1 ss/ pg ac20 v ddint h15 v ddmem u16 bmode0 g2 gnd k11 gnd ac23 pg3 f1 swe ab10 v ddint h16 v ddotp ac12 bmode1 f2 gnd k12 nc a15 pg4 d1 tck l1 v ddint j8 v ddrtc w23 bmode2 e1 gnd k13 nc a16 pg5 d2 tdi j1 v ddint j16 v ddusb w22 bmode3 e2 gnd k14 nc a17 pg6 c2 tdo k1 v ddint k8 v ddusb y23 clkbuf ab19 gnd k15 nc a18 pg7 b1 tms l2 v ddint k16 nc g23 clkin r23 gnd l9 nc a19 pg8 c1 trst k2 v ddint l8 vr out / ext_wake1 ac18 clkout ab18 gnd l10 nc a21 pg9 b2 usb_dm ab21 v ddint l16 vr sel / v ddext ab22 data0 y1 gnd l11 nc a22 pg10 b4 usb_dp aa22 v ddint m8 xtal p23 data1 v2 gnd l12 nc b20 pg11 b3 usb_id y22 v ddint m16 data2 w1 gnd l13 nc b21 pg12 a2 usb_rset ac21 v ddint n8 data3 u2 gnd l14 nc b23 pg13 a3 usb_vbus ab20 v ddint n16 data4 v1 gnd l15 nc c23 pg14 a4 usb_vref ac22 v ddint p8 data5 u1 gnd m9 nc d22 pg15 a5 usb_xi ab23 v ddint p16 note: in this table, bold type indicates the sole signal/function for that ball on adsp-bf522/adsp-bf524/adsp-bf526 processors. 1 for adsp-bf52xc compatibility, connect this ball to v ddext .
rev. d | page 81 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 68. 289-ball csp_bga ball assignme nt (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal a1 gnd b20 nc h12 v ddint l9 gnd p2 data10 t22 gnd ab10 swe a2 pg12 b21 nc h13 v ddint l10 gnd p7 v ddmem t23 ph9 ab11 vppotp a3 pg13 b22 scl h14 v ddint l11 gnd p8 v ddint u1 data5 ab12 sras a4 pg14 b23 nc h15 v ddint l12 gnd p9 gnd u2 data3 ab13 scke a5 pg15 c1 pg8 h16 v ddint l13 gnd p10 gnd u7 v ddmem ab14 awe a6 ppi_clk/tmrclk c2 pg6 h17 gnd 1 l14 gnd p11 gnd u8 v ddmem ab15 ams3 a7 pf0 c22 sda h22 gnd l15 gnd p12 gnd u9 v ddmem ab16 ams1 a8 pf2 c23 nc h23 nc l16 v ddint p13 gnd u10 v ddmem ab17 are a9 pf14 d1 pg4 j1 tdi l17 v ddext p14 gnd u11 v ddmem ab18 clkout a10 pf15 d2 pg5 j2 emu l22 ph8 p15 gnd u12 v ddmem ab19 clkbuf a11 ph0 d22 nc j7 v ddmem l23 ph7 p16 v ddint u13 v ddmem ab20 usb_vbus a12 ph1 d23 nc j8 v ddint m1 data15 p17 v ddext u14 v ddmem ab21 usb_dm a13 ph2 e1 bmode2 j9 gnd m2 data14 p22 ph15 u15 v ddmem ab22 vr sel / v ddext a14 ph4 e2 bmode3 j10 gnd m7 v ddmem p23 xtal u16 v ddmem ab23 usb_xi a15 nc e22 nc j11 gnd m8 v ddint r1 data8 u17 v ddext ac1 gnd a16 nc e23 nc j12 gnd m9 gnd r2 data11 u22 nmi ac2 addr14 a17 nc f1 pg3 j13 gnd m10 gnd r7 v ddmem u23 rtxi ac3 addr12 a18 nc f2 bmode1 j14 gnd m11 gnd r8 v ddint v1 data4 ac4 addr10 a19 nc f22 nc j15 gnd m12 gnd r9 gnd v2 data1 ac5 addr9 a20 pf9 f23 nc j16 v ddint m13 gnd r10 gnd v22 reset ac6 addr5 a21 nc g1 pg1 j17 v ddext m14 gnd r11 gnd v23 rtxo ac7 addr4 a22 nc g2 bmode0 j22 gnd 1 m15 gnd r12 gnd w1 data2 ac8 addr2 a23 gnd g7 v ddext j23 nc m16 v ddint r13 gnd w2 addr16 ac9 abe1 /sdqm1 b1 pg7 g8 v ddext k1 tdo m17 v ddext r14 gnd w22 v ddusb ac10 sa10 b2 pg9 g9 v ddext k2 trst m22 ph10 r15 gnd w23 v ddrtc ac11 scas b3 pg11 g10 v ddext k7 v ddmem m23 ph12 r16 v ddint y1 data0 ac12 v ddotp b4 pg10 g11 v ddext k8 v ddint n1 data12 r17 v ddext y2 addr17 ac13 sms b5 v ddint g12 v ddext k9 gnd n2 data13 r22 ph11 y22 usb_id ac14 ardy b6 gnd g13 v ddext k10 gnd n7 v ddmem r23clkin y23v ddusb ac15 aoe b7 ppi_fs1/tmr0 g14 v ddext k11 gnd n8 v ddint t1 data7 aa1 addr18 ac16 ams2 b8 pf1 g15 v ddext k12 gnd n9 gnd t2 data6 aa2 addr15 ac17 ams0 b9 pf3 g16 gnd 1 k13 gnd n10 gnd t7 v ddmem aa22 usb_dp ac18 vr out / ext_wake1 b10 pf5 g17 gnd k14 gnd n11 gnd t8 v ddint aa23 usb_xo ac19 ext_wake0 b11 pf4 g22 nc k15 gnd n12 gnd t9 v ddint ab1 addr19 ac20 ss/ pg b12 pf6 g23 nc k16 v ddint n13 gnd t10 v ddint ab2 addr13 ac21 usb_rset b13 pf7 h1 pg2 k17 v ddext n14 gnd t11 v ddint ab3 addr11 ac22 usb_vref b14 ph3 h2 pg0 k22 ph6 n15 gnd t12 v ddint ab4 addr7 ac23 gnd b15 pf10 h7 v ddext k23 ph5 n16 v ddint t13 v ddint ab5 addr8 b16 pf8 h8 v ddint l1 tck n17 v ddext t14 v ddint ab6 addr6 b17 pf11 h9 v ddint l2 tms n22 ph13 t15 v ddint ab7 addr3 b18 pf12 h10 v ddint l7 v ddmem n23 ph14 t16 v ddint ab8 addr1 b19 pf13 h11 v ddint l8 v ddint p1 data9 t17 v ddext ab9 abe0 /sdqm0 note: in this table, bold type indicates the sole signal/function for that ball on adsp-bf522/adsp-bf524/adsp-bf526 processors. 1 for adsp-bf52xc compatibility, connect this ball to v ddext .
rev. d | page 82 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 76 shows the top view of the bc-289-2 csp_bga ball configuration. figure 77 shows the bottom view of the bc-289-2 csp_bga ball configuration. figure 76. 289-ball csp_bga ba ll configuration (top view) figure 77. 289-ball csp_bga ball configuration (bottom view) top view a1 ball pad corner 345678910111213141516 1 2 17 18 19 20 21 22 23 m b c d e f g h j k l n r t a u v w y aa ab ac p key: v ddint gnd nc v ddext i/o v ddmem key: v ddint gnd nc v ddext i/o v ddmem bottom view a1 ball pad corner 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 17 18 19 20 21 22 23 m b c d e f g h j k l n r t a u v w y aa ab ac p
rev. d | page 83 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 208-ball csp_bga ball assignment table 69 lists the csp_bga balls by signal mnemonic. table 70 on page 84 lists the csp_bga by ball number. table 69. 208-ball csp_bga ball assign ment (alphabetica lly by signal) signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. abe0 /sdqm0 v19 clkout k20 gnd k11 pf13 a5 ppi_clk/tmrclk g2 v ddext j8 abe1 /sdqm1 v20 data0 y8 gnd k12 pf14 b6 ppi_fs1/tmr0 f2 v ddext k7 addr1 w20 data1 w8 gnd k13 pf15 a6 reset b18 v ddext k8 addr2 w19 data2 y7 gnd l9 pg0 r2 rtxi a14 v ddext l7 addr3 y19 data3 w7 gnd l10 pg1 p1 rtxo a15 v ddint g12 addr4 w18 data4 y6 gnd l11 pg2 p2 sa10 u19 v ddint g13 addr5 y18 data5 w6 gnd l12 pg3 n1 scas u20 v ddint g14 addr6 w17 data6 y5 gnd l13 pg4 n2 scke p20 v ddint h14 addr7 y17 data7 w5 gnd m9 pg5 m1 scl a4 v ddint j14 addr8 w16 data8 y4 gnd m10 pg6 m2 sda b4 v ddint k14 addr9 y16 data9 w4 gnd m11 pg7 l1 sms r19 v ddint l14 addr10 w15 data10 y3 gnd m12 pg8 l2 sras t19 v ddint m14 addr11 y15 data11 w3 gnd m13 pg9 k1 ss/ pg g19 v ddint n14 addr12 w14 data12 y2 gnd n9 pg10 k2 swe t20 v ddint p12 addr13 y14 data13 w2 gnd n10 pg11 j1 tck v2 v ddint p13 addr14 w13 data14 w1 gnd n11 pg12 j2 tdi r1 v ddint p14 addr15 y13 data15 v1 gnd n12 pg13 h1 tdo t1 v ddmem l8 addr16 w12 emu t2 gnd n13 pg14 h2 tms u2 v ddmem m7 addr17 y12 ext_wake0 j20 gnd y1 pg15 g1 trst u1 v ddmem m8 addr18 w11 gnd a1 gnd y20 ph0 a7 usb_dm f20 v ddmem n7 addr19 y11 gnd a17 nmi b19 ph1 b7 usb_dp e20 v ddmem n8 ams0 j19 gnd a20 vppotp l19 ph2 a8 usb_id c20 v ddmem p7 ams1 k19 gnd b20 pf0 f1 ph3 b8 usb_rset d20 v ddmem p8 ams2 m19 gnd h9 pf1 e1 ph4 a9 usb_vbus e19 v ddmem p9 ams3 l20 gnd h10 pf2 e2 ph5 b9 usb_vref h19 v ddmem p10 aoe n20 gnd h11 pf3 d1 ph6 b10 usb_xi a19 v ddmem p11 ardy p19 gnd h12 pf4 d2 ph7 b11 usb_xo a18 v ddotp r20 are m20 gnd h13 pf5 c1 ph8 a12 v ddext g7 v ddrtc a16 awe n19 gnd j9 pf6 c2 ph9 b12 v ddext g8 v ddusb d19 bmode0 y10 gnd j10 pf7 b1 ph10 a13 v ddext g9 v ddusb g20 bmode1 w10 gnd j11 pf8 b2 ph11 b13 v ddext g10 vr out / ext_wake1 h20 bmode2 y9 gnd j12 pf9 a2 ph12 b14 v ddext g11 vr sel / v ddext f19 bmode3 w9 gnd j13 pf10 b3 ph13 b15 v ddext h7 xtal a10 clkbuf c19 gnd k9 pf11 a3 ph14 b16 v ddext h8 clkin a11 gnd k10 pf12 b5 ph15 b17 v ddext j7 note: in this table, bold type indicates the sole signal/function for that ball on adsp-bf522/adsp-bf524/adsp-bf526 processors.
rev. d | page 84 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 table 70. 208-ball csp_bga ball assignme nt (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal ball no. signal a1 gnd b16 ph14 h7 v ddext l2 pg8 p1 pg1 w8 data1 a2 pf9 b17 ph15 h8 v ddext l7 v ddext p2 pg2 w9 bmode3 a3 pf11 b18 reset h9 gnd l8 v ddmem p7 v ddmem w10 bmode1 a4 scl b19 nmi h10 gnd l9 gnd p8 v ddmem w11 addr18 a5 pf13 b20 gnd h11 gnd l10 gnd p9 v ddmem w12 addr16 a6 pf15 c1 pf5 h12 gnd l11 gnd p10 v ddmem w13 addr14 a7 ph0 c2 pf6 h13 gnd l12 gnd p11 v ddmem w14 addr12 a8 ph2 c19 clkbuf h14 v ddint l13 gnd p12 v ddint w15 addr10 a9 ph4 c20 usb_id h19 usb_vref l14 v ddint p13 v ddint w16 addr8 a10 xtal d1 pf3 h20 vr out / ext_wake1 l19 vppotp p14 v ddint w17 addr6 a11 clkin d2 pf4 j1 pg11 l20 ams3 p19 ardy w18 addr4 a12 ph8 d19 v ddusb j2 pg12 m1 pg5 p20 scke w19 addr2 a13 ph10 d20 usb_rset j7 v ddext m2 pg6 r1 tdi w20 addr1 a14 rtxi e1 pf1 j8 v ddext m7 v ddmem r2 pg0 y1 gnd a15 rtxo e2 pf2 j9 gnd m8 v ddmem r19 sms y2 data12 a16 v ddrtc e19 usb_vbus j10 gnd m9 gnd r20 v ddotp y3 data10 a17 gnd e20 usb_dp j11 gnd m10 gnd t1 tdo y4 data8 a18 usb_xo f1 pf0 j12 gnd m11 gnd t2 emu y5 data6 a19 usb_xi f2 ppi_fs1/tmr0 j13 gnd m12 gnd t19 sras y6 data4 a20 gnd f19 vr sel / v ddext j14 v ddint m13 gnd t20 swe y7 data2 b1 pf7 f20 usb_dm j19 ams0 m14 v ddint u1 trst y8 data0 b2 pf8 g1 pg15 j20 ext_wake0 m19 ams2 u2 tms y9 bmode2 b3 pf10 g2 ppi_clk/tmrclk k1 pg9 m20 are u19 sa10 y10 bmode0 b4 sda g7 v ddext k2 pg10 n1 pg3 u20 scas y11 addr19 b5 pf12 g8 v ddext k7 v ddext n2 pg4 v1 data15 y12 addr17 b6 pf14 g9 v ddext k8 v ddext n7 v ddmem v2 tck y13 addr15 b7 ph1 g10 v ddext k9 gnd n8 v ddmem v19 abe0 /sdqm0 y14 addr13 b8 ph3 g11 v ddext k10 gnd n9 gnd v20 abe1 /sdqm1 y15 addr11 b9 ph5 g12 v ddint k11 gnd n10 gnd w1 data14 y16 addr9 b10 ph6 g13 v ddint k12 gnd n11 gnd w2 data13 y17 addr7 b11 ph7 g14 v ddint k13 gnd n12 gnd w3 data11 y18 addr5 b12 ph9 g19 ss/ pg k14 v ddint n13 gnd w4 data9 y19 addr3 b13 ph11 g20 v ddusb k19 ams1 n14 v ddint w5 data7 y20 gnd b14 ph12 h1 pg13 k20 clkout n19 awe w6 data5 b15 ph13 h2 pg14 l1 pg7 n20 aoe w7 data3 note: in this table, bold type indicates the sole signal/function for that ball on adsp-bf522/adsp-bf524/adsp-bf526 processors.
rev. d | page 85 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 figure 78 shows the top view of the csp_bga ball configura- tion. figure 79 shows the bottom view of the csp_bga ball configuration. figure 78. 208-ball csp_bga ba ll configuration (top view) figure 79. 208-ball csp_bga ball configuration (bottom view) 345678910111213141516 1 2 17 18 19 20 m b c d e f g h j k l n r t a u v w y p top view a1 ball pad corner key: vddint vddext vddmem gnd i/o 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 17 18 19 20 m b c d e f g h j k l n r t a u v w y p bottom view a1 ball pad corner key: vddint vddext vddmem gnd i/o
rev. d | page 86 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 outline dimensions dimensions in the outline dimension figures ( figure 80 and figure 81 ) are shown in millimeters. figure 80. 289-ball csp_bga (bc-289-2) figure 81. 208-ball csp_bga (bc-208-2) * compliant with jedec standard mo-275-ggce-1 0.50 bsc a b c d e f g h j k l m n p r 7 15 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 11.00 bsc sq 16 19 21 18 20 23 22 t u v w y aa ab ac 0.20 min detail a top view detail a coplanarity 0.08 0.35 0.30 0.25 ball diameter seating plane 12.00 bsc sq a1 ball corner 1.40 1.26 1.11 * compliant to jedec standards mo-275-mmab-1 with exception to package height and thickness. 0.35 nom 0.30 min * 1.75 1.61 1.46 * 1.36 1.26 1.16 a b c d e f g h j k l m n p r t u v w y 15 14 17 16 19 18 20 13 12 11 10 9 8 7 6 5 4 3 2 1 15.20 bsc sq 0.50 0.45 0.40 17.10 17.00 sq 16.90 coplanarity 0.12 ball diameter 0.80 bsc detail a a1 ball corner a1 ball corner detail a bottom view top view seating plane
rev. d | page 87 of 88 | july 2013 adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 surface-mount design table 71 is provided as an aid to pcb design. for industry-stan- dard design recommendations, refer to ipc-7351, generic requirements for surface mount design and land pattern standard . automotive products the adbf525w model is availabl e with controlled manufactur- ing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models and designers should review the product specifications section of this data sheet carefully. only the automotive grade products shown in table 72 are available for use in automotive applica- tions. contact your local adi acco unt representative for specific product ordering information and to obtain the specific auto- motive reliability reports for these models. table 71. surface-moun t design supplement package package ball attach type package solder mask opening package ball pad size 289-ball csp_bga solder mask defined 0. 26 mm diameter 0.35 mm diameter 208-ball csp_bga solder mask defined 0. 40 mm diameter 0.50 mm diameter table 72. automotive products automotive models 1, 2 temperature range 3 package description package option instruction rate (max) adbf525wbbcz4xx C40c to +85c 208-ball csp_bga bc-208-2 400 mhz adbf525wbbcz5xx C40c to +85c 208-ball csp_bga bc-208-2 533 mhz adbf525wybczxxx C40c to +105c 208- ball csp_bga bc-208-2 for product details, please contact your adi account representative. 1 z = rohs compliant part. 2 the information indicated by x in the model number will be provided by your adi account representative. 3 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions for adsp-bf523/adsp-bf525/ adsp-bf527 processors on page 30 for junction temperature (t j ) specification which is the on ly temperature specification.
rev. d | page 88 of 88 | july 2013 ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06675-0-7/13(d) adsp-bf522/adsp-bf523/adsp-bf524/adsp-bf525/adsp-bf526/adsp-bf527 ordering guide model 1 1 z = rohs compliant part. temperature range 2 2 referenced temperature is ambient temperature. the ambie nt temperature is not a sp ecification. please see operating conditions for ad sp-bf522/adsp-bf524/adsp-bf526 processors on page 28 and operating conditions for adsp-bf523/adsp -bf525/adsp-bf527 proc essors on page 30 for junction temperature (t j ) specification which is the only temperature specification. instruction rate (max) package description package option ADSP-BF522BBCZ-3A C40c to +85c 300 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf522bbcz-4a C40c to +85c 400 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf522kbcz-3 0c to +70c 300 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf522kbcz-4 0c to +70c 400 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf523bbcz-5a C40c to +85c 533 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf523kbcz-5 0c to +70c 533 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf523kbcz-6 0c to +70c 600 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf523kbcz-6a 0c to +70c 600 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf524bbcz-3a C40c to +85c 300 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf524bbcz-4a C40c to +85c 400 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf524kbcz-3 0c to +70c 300 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf524kbcz-4 0c to +70c 400 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf525abcz-5 C40c to +70c 500 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf525abcz-6 C40c to +70c 600 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf525bbcz-5a C40c to +85c 533 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf525kbcz-5 0c to +70c 533 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf525kbcz-6 0c to +70c 600 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf525kbcz-6a 0c to +70c 600 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf526bbcz-3a C40c to +85c 300 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf526bbcz-4a C40c to +85c 400 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf526kbcz-3 0c to +70c 300 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf526kbcz-4 0c to +70c 400 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf527bbcz-5a C40c to +85c 533 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2 adsp-bf527kbcz-5 0c to +70c 533 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf527kbcz-6 0c to +70c 600 mhz 289-ball chip scale package ball grid array (csp_bga) bc-289-2 adsp-bf527kbcz-6a 0c to +70c 600 mhz 208-ball chip scale package ball grid array (csp_bga) bc-208-2

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